Mathias Nyman <mathias.ny...@linux.intel.com> writes:

> The USB 3.2 specification adds support for Dual-lane, doubling the
> maximum rate to 20Gbps by taking into use another set of rx and tx
> wires and pins in the Type-C cable and connector.
> The changes to support this in USB core and xhci driver seems to be minor.
> USB 3.1 support already added the extended port status request returning
> lane count. it just wasn't used before.
> I'd like to use these patches to start a discussion about which items
> regarding Dual-lane and USB 3.2 should be exposed to userspace and how.
> These patches add a variable "lanes" to store the number of lanes
> in use, and adds the Gen XxY notion to the string displayed when a new
> device is connected. X in Gen XxY stands for signaling rate,
> Y for lane count, as described in the USB 3.2 specification.
> Example for clarification:
> Gen 1x1 = 5Gbps, SuperSpeed, one lane, same as USB3.0, and USB 3.1 Gen1
> Gen 2x1 = 10Gbps, SuperSpeedPlus, one lane, same as USB 3.1 Gen2
> Gen 1x2 = 10Gbps, SuperSpeed, Dual-lane (2 x 5Gbps)
> Gen 2x2 = 20Gbps, SuperSpeedPlus, Dual-lane (2 x 10Gbps)

it's a little more interesting than that, no?

IIRC, we can Gen 2x2 RX and Gen 2x1 TX (and vice-versa).

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