On Sun, 2013-09-29 at 12:19 -0300, Fabio Estevam wrote:
> On Sun, Sep 29, 2013 at 11:32 AM, Christoph Fritz
> <chf.fr...@googlemail.com> wrote:
> >> Le 26/09/2013 17:59, Christoph Fritz a écrit :
> >> > Their software fix:
> >> > "As first attemp at fixing this issue, one may try to switch LINK to
> >> > ULPI mode before configuring MUX and pads for USB operation. Fear is
> >> > that this could cause unexpected transfer from PHY to LINK, somehow
> >> > preventing proper initialization"
> >> >
> >> > I'll try that here with the smsc3340-phy.
> >
> > What a mess, it is also important in what order the muxing of USB-Pins
> > is done beside the fact that some USBOTG pins had a GPIO_OUT configured
> > wrongly. Don't ask how I hit this, but with that and the info from above
> > finally both smsc3340 phys on OTG and USBH2 get detected: pure
>
> Can you show a patch or code so that others could fix this problem as well?
Sure, attached to this mail are 4 of my work-in-progress patches, two
for barebox and two for the kernel. Consider them RFC. The ULPI-mode
switching before muxing is already part of barebox.
Thanks
-- Christoph
>From a5f16b4cee15ea239d90bc4c18db3d9628afecec Mon Sep 17 00:00:00 2001
From: Christoph Fritz <chf.fr...@googlemail.com>
Date: Sat, 28 Sep 2013 12:41:30 +0200
Subject: [PATCH 2/2] i.MX27: fix USBOTG muxing
Signed-off-by: Christoph Fritz <chf.fr...@googlemail.com>
---
arch/arm/mach-imx/include/mach/iomux-mx27.h | 24 ++++++++++++------------
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/arch/arm/mach-imx/include/mach/iomux-mx27.h b/arch/arm/mach-imx/include/mach/iomux-mx27.h
index 23e448b..6ff8651 100644
--- a/arch/arm/mach-imx/include/mach/iomux-mx27.h
+++ b/arch/arm/mach-imx/include/mach/iomux-mx27.h
@@ -38,13 +38,13 @@
#define PB25_PF_USBH1_RCV (GPIO_PORTB | GPIO_PF | 25)
#define PC5_PF_I2C2_SDA (GPIO_PORTC | GPIO_PF | GPIO_IN | 5)
#define PC6_PF_I2C2_SCL (GPIO_PORTC | GPIO_PF | GPIO_IN | 6)
-#define PC7_PF_USBOTG_DATA5 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 7)
-#define PC8_PF_USBOTG_DATA6 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 8)
-#define PC9_PF_USBOTG_DATA0 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 9)
-#define PC10_PF_USBOTG_DATA2 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 10)
-#define PC11_PF_USBOTG_DATA1 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 11)
-#define PC12_PF_USBOTG_DATA4 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 12)
-#define PC13_PF_USBOTG_DATA3 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 13)
+#define PC7_PF_USBOTG_DATA5 (GPIO_PORTC | GPIO_PF | 7)
+#define PC8_PF_USBOTG_DATA6 (GPIO_PORTC | GPIO_PF | 8)
+#define PC9_PF_USBOTG_DATA0 (GPIO_PORTC | GPIO_PF | 9)
+#define PC10_PF_USBOTG_DATA2 (GPIO_PORTC | GPIO_PF | 10)
+#define PC11_PF_USBOTG_DATA1 (GPIO_PORTC | GPIO_PF | 11)
+#define PC12_PF_USBOTG_DATA4 (GPIO_PORTC | GPIO_PF | 12)
+#define PC13_PF_USBOTG_DATA3 (GPIO_PORTC | GPIO_PF | 13)
#define PC16_PF_SSI4_FS (GPIO_PORTC | GPIO_PF | GPIO_IN | 16)
#define PC17_PF_SSI4_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 17)
#define PC18_PF_SSI4_TXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 18)
@@ -66,11 +66,11 @@
#define PD14_PF_ATA_DATA12 (GPIO_PORTD | GPIO_PF | 14)
#define PD15_PF_ATA_DATA13 (GPIO_PORTD | GPIO_PF | 15)
#define PD16_PF_ATA_DATA14 (GPIO_PORTD | GPIO_PF | 16)
-#define PE0_PF_USBOTG_NXT (GPIO_PORTE | GPIO_PF | GPIO_OUT | 0)
-#define PE1_PF_USBOTG_STP (GPIO_PORTE | GPIO_PF | GPIO_OUT | 1)
-#define PE2_PF_USBOTG_DIR (GPIO_PORTE | GPIO_PF | GPIO_OUT | 2)
-#define PE24_PF_USBOTG_CLK (GPIO_PORTE | GPIO_PF | GPIO_OUT | 24)
-#define PE25_PF_USBOTG_DATA7 (GPIO_PORTE | GPIO_PF | GPIO_OUT | 25)
+#define PE0_PF_USBOTG_NXT (GPIO_PORTE | GPIO_PF | 0)
+#define PE1_PF_USBOTG_STP (GPIO_PORTE | GPIO_PF | 1)
+#define PE2_PF_USBOTG_DIR (GPIO_PORTE | GPIO_PF | 2)
+#define PE24_PF_USBOTG_CLK (GPIO_PORTE | GPIO_PF | 24)
+#define PE25_PF_USBOTG_DATA7 (GPIO_PORTE | GPIO_PF | 25)
#define PF1_PF_NFCLE (GPIO_PORTF | GPIO_PF | 1)
#define PF3_PF_NFCE (GPIO_PORTF | GPIO_PF | 3)
#define PF7_PF_PC_POE (GPIO_PORTF | GPIO_PF | 7)
--
1.7.10.4
>From d6390bcfa4435af350f3c76a369954824fec76ea Mon Sep 17 00:00:00 2001
From: Christoph Fritz <chf.fr...@googlemail.com>
Date: Fri, 27 Sep 2013 17:07:43 +0200
Subject: [PATCH 1/2] ARM: pca100: fix USB muxing order
The order of muxing USB-Pins seems to be important when ULPI-Mode
is configured. ULPI-Mode is and needs to be set before muxing, which
is already done for pca100.
Signed-off-by: Christoph Fritz <chf.fr...@googlemail.com>
---
arch/arm/boards/phycard-i.MX27/pca100.c | 40 +++++++++++++++++++++----------
1 file changed, 27 insertions(+), 13 deletions(-)
diff --git a/arch/arm/boards/phycard-i.MX27/pca100.c b/arch/arm/boards/phycard-i.MX27/pca100.c
index 8ea7b0d..03be662 100644
--- a/arch/arm/boards/phycard-i.MX27/pca100.c
+++ b/arch/arm/boards/phycard-i.MX27/pca100.c
@@ -201,6 +201,33 @@ static int pca100_devices_init(void)
struct device_d *nand;
unsigned int mode[] = {
+ /* USB host 2 */
+ PA2_PF_USBH2_DATA7,
+ PD21_AF_USBH2_DATA6,
+ PD26_AF_USBH2_DATA5,
+ PD19_AF_USBH2_DATA4,
+ PD20_AF_USBH2_DATA3,
+ PD23_AF_USBH2_DATA2,
+ PD24_AF_USBH2_DATA1,
+ PD22_AF_USBH2_DATA0,
+ PA4_PF_USBH2_STP,
+ PA3_PF_USBH2_NXT,
+ PA1_PF_USBH2_DIR,
+ PA0_PF_USBH2_CLK,
+ /* OTG */
+ PE25_PF_USBOTG_DATA7,
+ PC8_PF_USBOTG_DATA6,
+ PC7_PF_USBOTG_DATA5,
+ PC12_PF_USBOTG_DATA4,
+ PC13_PF_USBOTG_DATA3,
+ PC10_PF_USBOTG_DATA2,
+ PC11_PF_USBOTG_DATA1,
+ PC9_PF_USBOTG_DATA0,
+ PE1_PF_USBOTG_STP,
+ PE0_PF_USBOTG_NXT,
+ PE2_PF_USBOTG_DIR,
+ PE24_PF_USBOTG_CLK,
+ /* div */
PD0_AIN_FEC_TXD0,
PD1_AIN_FEC_TXD1,
PD2_AIN_FEC_TXD2,
@@ -230,19 +257,6 @@ static int pca100_devices_init(void)
PD29_PF_CSPI1_SCLK,
PD30_PF_CSPI1_MISO,
PD31_PF_CSPI1_MOSI,
- /* USB host 2 */
- PA0_PF_USBH2_CLK,
- PA1_PF_USBH2_DIR,
- PA2_PF_USBH2_DATA7,
- PA3_PF_USBH2_NXT,
- PA4_PF_USBH2_STP,
- PD19_AF_USBH2_DATA4,
- PD20_AF_USBH2_DATA3,
- PD21_AF_USBH2_DATA6,
- PD22_AF_USBH2_DATA0,
- PD23_AF_USBH2_DATA2,
- PD24_AF_USBH2_DATA1,
- PD26_AF_USBH2_DATA5,
/* SDHC */
PB4_PF_SD2_D0,
PB5_PF_SD2_D1,
--
1.7.10.4
>From 652737fabe45d3f657ae93cc9a63555223291eec Mon Sep 17 00:00:00 2001
From: Christoph Fritz <chf.fr...@googlemail.com>
Date: Sat, 28 Sep 2013 12:47:25 +0200
Subject: [PATCH 2/2] arm: pca100: change USB muxing order for prone ULPI
connections
Reset mode of USBH2 and OTG is serial instead of ULPI (TRM: 30.6.7
ULPI/Serial MUX). Due to the fact that pca100 is equipped with two
USB-ULPI-phys, requires a delicate initialization:
1. set USB to ULPI-mode
2. do muxing in correct order (CLK as last pin)
The initialization is alreday done by the bootloader, even the muxing.
This patch resembles the configuration of muxing already done by the
bootloader to keep it in sync and avoid confusion.
Signed-off-by: Christoph Fritz <chf.fr...@googlemail.com>
---
arch/arm/mach-imx/mach-pca100.c | 45 +++++++++++++++++++--------------------
1 file changed, 22 insertions(+), 23 deletions(-)
diff --git a/arch/arm/mach-imx/mach-pca100.c b/arch/arm/mach-imx/mach-pca100.c
index 29c6303..d3cb1a1 100644
--- a/arch/arm/mach-imx/mach-pca100.c
+++ b/arch/arm/mach-imx/mach-pca100.c
@@ -105,34 +105,34 @@ static const int pca100_pins[] __initconst = {
PD29_PF_CSPI1_SCLK,
PD30_PF_CSPI1_MISO,
PD31_PF_CSPI1_MOSI,
+ /* USBH2 */
+ USBH2_PHY_CS_GPIO | GPIO_GPIO | GPIO_OUT,
+ PA2_PF_USBH2_DATA7,
+ PD21_AF_USBH2_DATA6,
+ PD26_AF_USBH2_DATA5,
+ PD19_AF_USBH2_DATA4,
+ PD20_AF_USBH2_DATA3,
+ PD23_AF_USBH2_DATA2,
+ PD24_AF_USBH2_DATA1,
+ PD22_AF_USBH2_DATA0,
+ PA4_PF_USBH2_STP,
+ PA3_PF_USBH2_NXT,
+ PA1_PF_USBH2_DIR,
+ PA0_PF_USBH2_CLK,
/* OTG */
OTG_PHY_CS_GPIO | GPIO_GPIO | GPIO_OUT,
- PC7_PF_USBOTG_DATA5,
+ PE25_PF_USBOTG_DATA7,
PC8_PF_USBOTG_DATA6,
- PC9_PF_USBOTG_DATA0,
- PC10_PF_USBOTG_DATA2,
- PC11_PF_USBOTG_DATA1,
+ PC7_PF_USBOTG_DATA5,
PC12_PF_USBOTG_DATA4,
PC13_PF_USBOTG_DATA3,
- PE0_PF_USBOTG_NXT,
+ PC10_PF_USBOTG_DATA2,
+ PC11_PF_USBOTG_DATA1,
+ PC9_PF_USBOTG_DATA0,
PE1_PF_USBOTG_STP,
+ PE0_PF_USBOTG_NXT,
PE2_PF_USBOTG_DIR,
PE24_PF_USBOTG_CLK,
- PE25_PF_USBOTG_DATA7,
- /* USBH2 */
- USBH2_PHY_CS_GPIO | GPIO_GPIO | GPIO_OUT,
- PA0_PF_USBH2_CLK,
- PA1_PF_USBH2_DIR,
- PA2_PF_USBH2_DATA7,
- PA3_PF_USBH2_NXT,
- PA4_PF_USBH2_STP,
- PD19_AF_USBH2_DATA4,
- PD20_AF_USBH2_DATA3,
- PD21_AF_USBH2_DATA6,
- PD22_AF_USBH2_DATA0,
- PD23_AF_USBH2_DATA2,
- PD24_AF_USBH2_DATA1,
- PD26_AF_USBH2_DATA5,
/* display */
PA5_PF_LSCLK,
PA6_PF_LD0,
@@ -717,10 +717,10 @@ static void __init pca100_init(void)
gpio_request(USBH2_PHY_CS_GPIO, "usb-host2-cs");
gpio_direction_output(USBH2_PHY_CS_GPIO, 1);
+ /* OTG */
if (otg_mode_host) {
otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
ULPI_OTG_DRVVBUS_EXT);
-
if (otg_pdata.otg)
imx27_add_mxc_ehci_otg(&otg_pdata);
} else {
@@ -728,14 +728,13 @@ static void __init pca100_init(void)
imx27_add_fsl_usb2_udc(&otg_device_pdata);
}
+ /* USBH2 */
usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
-
if (usbh2_pdata.otg)
imx27_add_mxc_ehci_hs(2, &usbh2_pdata);
imx27_add_imx_fb(&pca100_fb_data);
-
imx27_add_fec(NULL);
imx27_add_imx2_wdt(NULL);
imx27_add_mxc_w1(NULL);
--
1.7.10.4
>From fd3c742edc828006021074b0107505d1b72ee964 Mon Sep 17 00:00:00 2001
From: Christoph Fritz <chf.fr...@googlemail.com>
Date: Sat, 28 Sep 2013 12:45:01 +0200
Subject: [PATCH 1/2] arm: mx27: set USBOTG muxing to correct primary function
Configure correct primary direction for USBOTG-pin direction.
TRM: 30.6.3.4 OTG Port Signal Connections and Signal Muxing
TRM: Table 5-2. i.MX27 Pin MUX Table
Signed-off-by: Christoph Fritz <chf.fr...@googlemail.com>
---
arch/arm/plat-mxc/include/mach/iomux-mx27.h | 24 ++++++++++++------------
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx27.h b/arch/arm/plat-mxc/include/mach/iomux-mx27.h
index d9f9a6e..eb44919 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx27.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx27.h
@@ -33,13 +33,13 @@
#define PB25_PF_USBH1_RCV (GPIO_PORTB | GPIO_PF | 25)
#define PC5_PF_I2C2_SDA (GPIO_PORTC | GPIO_PF | GPIO_IN | 5)
#define PC6_PF_I2C2_SCL (GPIO_PORTC | GPIO_PF | GPIO_IN | 6)
-#define PC7_PF_USBOTG_DATA5 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 7)
-#define PC8_PF_USBOTG_DATA6 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 8)
-#define PC9_PF_USBOTG_DATA0 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 9)
-#define PC10_PF_USBOTG_DATA2 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 10)
-#define PC11_PF_USBOTG_DATA1 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 11)
-#define PC12_PF_USBOTG_DATA4 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 12)
-#define PC13_PF_USBOTG_DATA3 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 13)
+#define PC7_PF_USBOTG_DATA5 (GPIO_PORTC | GPIO_PF | 7)
+#define PC8_PF_USBOTG_DATA6 (GPIO_PORTC | GPIO_PF | 8)
+#define PC9_PF_USBOTG_DATA0 (GPIO_PORTC | GPIO_PF | 9)
+#define PC10_PF_USBOTG_DATA2 (GPIO_PORTC | GPIO_PF | 10)
+#define PC11_PF_USBOTG_DATA1 (GPIO_PORTC | GPIO_PF | 11)
+#define PC12_PF_USBOTG_DATA4 (GPIO_PORTC | GPIO_PF | 12)
+#define PC13_PF_USBOTG_DATA3 (GPIO_PORTC | GPIO_PF | 13)
#define PC16_PF_SSI4_FS (GPIO_PORTC | GPIO_PF | GPIO_IN | 16)
#define PC17_PF_SSI4_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 17)
#define PC18_PF_SSI4_TXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 18)
@@ -61,11 +61,11 @@
#define PD14_PF_ATA_DATA12 (GPIO_PORTD | GPIO_PF | 14)
#define PD15_PF_ATA_DATA13 (GPIO_PORTD | GPIO_PF | 15)
#define PD16_PF_ATA_DATA14 (GPIO_PORTD | GPIO_PF | 16)
-#define PE0_PF_USBOTG_NXT (GPIO_PORTE | GPIO_PF | GPIO_OUT | 0)
-#define PE1_PF_USBOTG_STP (GPIO_PORTE | GPIO_PF | GPIO_OUT | 1)
-#define PE2_PF_USBOTG_DIR (GPIO_PORTE | GPIO_PF | GPIO_OUT | 2)
-#define PE24_PF_USBOTG_CLK (GPIO_PORTE | GPIO_PF | GPIO_OUT | 24)
-#define PE25_PF_USBOTG_DATA7 (GPIO_PORTE | GPIO_PF | GPIO_OUT | 25)
+#define PE0_PF_USBOTG_NXT (GPIO_PORTE | GPIO_PF | 0)
+#define PE1_PF_USBOTG_STP (GPIO_PORTE | GPIO_PF | 1)
+#define PE2_PF_USBOTG_DIR (GPIO_PORTE | GPIO_PF | 2)
+#define PE24_PF_USBOTG_CLK (GPIO_PORTE | GPIO_PF | 24)
+#define PE25_PF_USBOTG_DATA7 (GPIO_PORTE | GPIO_PF | 25)
#define PF1_PF_NFCLE (GPIO_PORTF | GPIO_PF | 1)
#define PF3_PF_NFCE (GPIO_PORTF | GPIO_PF | 3)
#define PF7_PF_PC_POE (GPIO_PORTF | GPIO_PF | 7)
--
1.7.10.4
