On Wed, Oct 26, 2016 at 01:17:36PM -0700, Brian Norris wrote: > Hi Rajat, > > On Fri, Oct 21, 2016 at 02:21:09PM -0700, Rajat Jain wrote: > > From: Xinming Hu <h...@marvell.com> > > > > This patch derives device tree node from pcie bus layer framework, and > > fixes a minor memory leak in mwifiex_pcie_probe() (in failure path). > > Device tree bindings file has been renamed(marvell-sd8xxx.txt -> > > marvell-8xxx.txt) to accommodate PCIe changes. > > > > Signed-off-by: Xinming Hu <h...@marvell.com> > > Signed-off-by: Amitkumar Karwar <akar...@marvell.com> > > Signed-off-by: Rajat Jain <raja...@google.com> > > Reviewed-by: Brian Norris <briannor...@chromium.org> > > --- > > v2: Included vendor and product IDs in compatible strings for PCIe > > chipsets(Rob Herring) > > v3: Patch is created using -M option so that it will only include diff of > > original and renamed files(Rob Herring) > > Resend v3: Resending the patch because I missed to include device tree > > mailing > > while sending v3. > > v4: Fix error handling, also move-on even if no device tree node is present. > > v5: Update commit log to include memory leak, return -EINVAL instead of -1. > > I've been working on reworking some bugfixes for this driver, and I > noticed we have some problems w.r.t. memory leaks, and the "memory leak" > fix is not actually a fix. See below.
Sorry, I just saw this... Why do we need devicetree data for discoverable bus (PCI)? How does the driver work on systems that do not use DT? Why do we need them to behave differently? Thanks. -- Dmitry
