Based on FPGA hw design that includes sgmii ethernet feature, add corresponding dts file to enable ethernet port on agilex board. Create this dts file refer to below links from Intel SoC PFGA Community https://releases.rocketboards.org/release/dts-source/agilex/ https://releases.rocketboards.org/release/2021.11/dts-source/agilex/gsrd/
Signed-off-by: Meng Li <[email protected]> --- .../dts/intel/socfpga_agilex_socdk_sgmii.dts | 55 +++++++++++++++++++ 1 file changed, 55 insertions(+) create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex_socdk_sgmii.dts diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk_sgmii.dts b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk_sgmii.dts new file mode 100644 index 000000000000..65bb04a46fb7 --- /dev/null +++ b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk_sgmii.dts @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021, Intel Corporation + */ + +#include "socfpga_agilex_socdk.dts" + +/{ + soc { + clocks { + sgmii_1_clk_0: sgmii_1_clk_0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; /* 125.00 MHz */ + clock-output-names = "sgmii_1_clk_0-out_clk"; + }; //end sgmii_1_clk_0 (sgmii_1_clk_0) + + sgmii_1_clk_125: sgmii_1_clk_125 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; /* 125.00 MHz */ + clock-output-names = "sgmii_1_clk_125-out_clk"; + }; //end sgmii_1_clk_125 (sgmii_1_clk_125) + }; + + s10_hps_bridges: bridge@80000000 { + compatible = "altr,bridge-18.1", "simple-bus"; + reg = <0x80000000 0x60000000>, + <0xf9000000 0x00100000>; + reg-names = "axi_h2f", "axi_h2f_lw"; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0x00000000 0x00000000 0x80000000 0x00040000>, + <0x00000001 0x00000000 0xf9003000 0x00000040>, + <0x00000001 0x00000040 0xf9003040 0x00000008>; + + sgmii_1_gmii2sgmii: phy@100000000 { + compatible = "altr,gmii-to-sgmii-2.0"; + reg = <0x00000001 0x00000000 0x00000040>, + <0x00000001 0x00000040 0x00000008>; + reg-names = "eth_tse_control_port", "gmii_to_sgmii_adapter_avalon_slave"; + clocks = <&sgmii_1_clk_0 &gmac1 1 &sgmii_1_clk_125 &sgmii_1_clk_125>; + clock-names = "clock_in", "emac_gtx_clk", "tse_pcs_ref_clk_clock_connection", "tse_rx_cdr_refclk"; + }; //end phy@0x100000040 (sgmii_1_gmii2sgmii) + }; + + }; +}; + +&gmac1 { + altr,gmii-to-sgmii-converter = <&sgmii_1_gmii2sgmii>; + #clock-cells = <1>; + phy-mode = "sgmii"; + status = "okay"; +}; -- 2.17.1
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