From: Teh Wen Ping <[email protected]> commit 4b1732303c1f0e9b9b3de9fdb43edff5449cfc90 from https://github.com/altera-opensource/linux-socfpga.git
Change COMMAND_POLL_SERVICE_STATUS interval into two interval. Poll the status every 20ms for 1sec and if status is still not ready, poll every 500ms for 29sec. Fast response commands will have shorter latency. Signed-off-by: Teh Wen Ping <[email protected]> Signed-off-by: Wenlin Kang <[email protected]> --- drivers/firmware/stratix10-svc.c | 94 ++++++++++++++++++++++---------- 1 file changed, 66 insertions(+), 28 deletions(-) diff --git a/drivers/firmware/stratix10-svc.c b/drivers/firmware/stratix10-svc.c index a291e38520bc..5036d8e2a183 100644 --- a/drivers/firmware/stratix10-svc.c +++ b/drivers/firmware/stratix10-svc.c @@ -29,14 +29,25 @@ * from the secure world for FPGA manager to reuse, or to free the buffer(s) * when all bit-stream data had be send. * - * FPGA_CONFIG_STATUS_TIMEOUT_SEC - poll the FPGA configuration status, - * service layer will return error to FPGA manager when timeout occurs, - * timeout is set to 30 seconds (30 * 1000) at Intel Stratix10 SoC. + * FPGA_CONFIG_POLL_INTERVAL_MS_FAST - interval for polling the service status + * at secure world for fast response commands. Interval is set to 20ms. + * + * FPGA_CONFIG_POLL_INTERVAL_MS_SLOW - interval for polling the service status + * at secure world for slow response commands. Interval is set to 500ms. + * + * FPGA_CONFIG_POLL_COUNT_FAST - number of count for polling service status for + * fast response commands. Count is set to 50 (50*20ms=1sec) + * + * FPGA_CONFIG_POLL_COUNT_SLOW - number of count for polling service status for + * slow response commands. Count is set to 58 (58*500ms=29sec) */ #define SVC_NUM_DATA_IN_FIFO 8 #define SVC_NUM_CHANNEL 4 #define FPGA_CONFIG_DATA_CLAIM_TIMEOUT_MS 2000 -#define FPGA_CONFIG_STATUS_TIMEOUT_SEC 30 +#define FPGA_CONFIG_POLL_INTERVAL_MS_FAST 20 +#define FPGA_CONFIG_POLL_INTERVAL_MS_SLOW 500 +#define FPGA_CONFIG_POLL_COUNT_FAST 50 +#define FPGA_CONFIG_POLL_COUNT_SLOW 58 #define BYTE_TO_WORD_SIZE 4 /* stratix10 service layer clients */ @@ -255,6 +266,47 @@ static void svc_thread_cmd_data_claim(struct stratix10_svc_controller *ctrl, wait_for_completion_timeout(&ctrl->complete_status, timeout)); } +/** + * svc_cmd_poll_status() - poll for status + * @p_data: pointer to service data structure + * @ctrl: pointer to service layer controller + * @res: pointer to store response + * @poll_count: pointer to poll count value + * @poll_interval_in_ms: interval value in miliseconds + * + * Check whether the service at secure world has completed, and then inform the + * response. + */ +static void svc_cmd_poll_status(struct stratix10_svc_data *p_data, + struct stratix10_svc_controller *ctrl, + struct arm_smccc_res *res, + int *poll_count, int poll_interval_in_ms) +{ + unsigned long a0, a1, a2; + + a0 = INTEL_SIP_SMC_FPGA_CONFIG_ISDONE; + a1 = (unsigned long)p_data->paddr; + a2 = (unsigned long)p_data->size; + + if (p_data->command == COMMAND_POLL_SERVICE_STATUS) + a0 = INTEL_SIP_SMC_SERVICE_COMPLETED; + + while (*poll_count) { + ctrl->invoke_fn(a0, a1, a2, 0, 0, 0, 0, 0, res); + if ((res->a0 == INTEL_SIP_SMC_STATUS_OK) || + (res->a0 == INTEL_SIP_SMC_STATUS_ERROR) || + (res->a0 == INTEL_SIP_SMC_STATUS_REJECTED)) + break; + + /* + * request is still in progress, go to sleep then + * poll again + */ + msleep(poll_interval_in_ms); + (*poll_count)--; + } +} + /** * svc_thread_cmd_config_status() - check configuration status * @ctrl: pointer to service layer controller @@ -269,8 +321,7 @@ static void svc_thread_cmd_config_status(struct stratix10_svc_controller *ctrl, struct stratix10_svc_cb_data *cb_data) { struct arm_smccc_res res; - int count_in_sec; - unsigned long a0, a1, a2; + int poll_count; cb_data->kaddr1 = NULL; cb_data->kaddr2 = NULL; @@ -280,30 +331,17 @@ static void svc_thread_cmd_config_status(struct stratix10_svc_controller *ctrl, /* for debug purpose only */ pr_debug("%s: polling completed status\n", __func__); - a0 = INTEL_SIP_SMC_FPGA_CONFIG_ISDONE; - a1 = (unsigned long)p_data->paddr; - a2 = (unsigned long)p_data->size; - - if (p_data->command == COMMAND_POLL_SERVICE_STATUS) - a0 = INTEL_SIP_SMC_SERVICE_COMPLETED; - - count_in_sec = FPGA_CONFIG_STATUS_TIMEOUT_SEC; - while (count_in_sec) { - ctrl->invoke_fn(a0, a1, a2, 0, 0, 0, 0, 0, &res); - if ((res.a0 == INTEL_SIP_SMC_STATUS_OK) || - (res.a0 == INTEL_SIP_SMC_STATUS_ERROR) || - (res.a0 == INTEL_SIP_SMC_STATUS_REJECTED)) - break; - - /* - * request is still in progress, wait one second then - * poll again - */ - msleep(1000); - count_in_sec--; + poll_count = FPGA_CONFIG_POLL_COUNT_FAST; + svc_cmd_poll_status(p_data, ctrl, &res, &poll_count, + FPGA_CONFIG_POLL_INTERVAL_MS_FAST); + /* Inceased poll interval if response is still not ready */ + if (!poll_count) { + poll_count = FPGA_CONFIG_POLL_COUNT_SLOW; + svc_cmd_poll_status(p_data, ctrl, &res, &poll_count, + FPGA_CONFIG_POLL_INTERVAL_MS_SLOW); } - if (!count_in_sec) { + if (!poll_count) { pr_err("%s: poll status timeout\n", __func__); cb_data->status = BIT(SVC_STATUS_BUSY); } else if (res.a0 == INTEL_SIP_SMC_STATUS_OK) { -- 2.25.1
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