Previous commit 2d37482e0bed(phy: lynx-28g: add support for backplane modes
through PHY_MODE_ETHERNET_LINKMODE) added redefined macros and function
definitions,
This causes below building issues:
drivers/phy/freescale/phy-fsl-lynx-28g.c:1523:13: error: redefinition of
'lynx_28g_remove'
| 1523 | static void lynx_28g_remove(struct platform_device *pdev)
| | ^~~~~~~~~~~~~~~
drivers/phy/freescale/phy-fsl-lynx-28g.c:443:6: error: redeclaration of 'enum
lynx_28g_eq_type'
| 443 | enum lynx_28g_eq_type {
| | ^~~~~~~~~~~~~~~~
And move the static function lynx_28g_snapshot_rx_eq_gains() to before
use.
Signed-off-by: Xulin Sun <xulin....@windriver.com>
---
drivers/phy/freescale/phy-fsl-lynx-28g.c | 169 +++++------------------
1 file changed, 36 insertions(+), 133 deletions(-)
mode change 100644 => 100755 drivers/phy/freescale/phy-fsl-lynx-28g.c
diff --git a/drivers/phy/freescale/phy-fsl-lynx-28g.c
b/drivers/phy/freescale/phy-fsl-lynx-28g.c
old mode 100644
new mode 100755
index 5cb34312d593..5051609d373d
--- a/drivers/phy/freescale/phy-fsl-lynx-28g.c
+++ b/drivers/phy/freescale/phy-fsl-lynx-28g.c
@@ -129,20 +129,6 @@
#define LYNX_28G_LNaTECR1_EQ_ADPT_EQ(x) (((x) << 24) &
LYNX_28G_LNaTECR1_EQ_ADPT_EQ_MSK)
#define LYNX_28G_LNaTECR1_EQ_ADPT_EQ_X(x) (((x) &
LYNX_28G_LNaTECR1_EQ_ADPT_EQ_MSK) >> 24)
-#define LYNX_28G_LNaTECR0_EQ_TYPE(x) (((x) << 28) & GENMASK(30, 28))
-#define LYNX_28G_LNaTECR0_EQ_TYPE_X(x) (((x) & GENMASK(30, 28)) >> 28)
-#define LYNX_28G_LNaTECR0_EQ_SGN_PREQ BIT(23)
-#define LYNX_28G_LNaTECR0_EQ_PREQ(x) (((x) << 16) & GENMASK(19, 16))
-#define LYNX_28G_LNaTECR0_EQ_PREQ_X(x) (((x) & GENMASK(19, 16)) >> 16)
-#define LYNX_28G_LNaTECR0_EQ_SGN_POST1Q BIT(15)
-#define LYNX_28G_LNaTECR0_EQ_POST1Q(x) (((x) << 8) & GENMASK(12, 8))
-#define LYNX_28G_LNaTECR0_EQ_POST1Q_X(x) (((x) & GENMASK(12, 8))
>> 8)
-#define LYNX_28G_LNaTECR0_EQ_AMP_RED(x) ((x) & GENMASK(5, 0))
-
-#define LYNX_28G_LNaTECR1_EQ_ADPT_EQ_DRVR_DIS BIT(31)
-#define LYNX_28G_LNaTECR1_EQ_ADPT_EQ(x) (((x) << 24) &
GENMASK(29, 24))
-#define LYNX_28G_LNaTECR1_EQ_ADPT_EQ_X(x) (((x) & GENMASK(29, 24)) >> 24)
-
/* Lane a Rx Reset Control Register */
#define LYNX_28G_LNaRRSTCTL(lane) (0x800 + (lane) * 0x100 + 0x40)
#define LYNX_28G_LNaRRSTCTL_DIS BIT(24)
@@ -185,23 +171,6 @@
#define LYNX_28G_LNaRGCR1_CHANGE_RX_CLK BIT(3)
#define LYNX_28G_LNaRGCR1_PWR_MGT(x) ((x) & GENMASK(2, 0))
-#define LYNX_28G_LNaRGCR1_RX_ORD_ELECIDLE BIT(31)
-#define LYNX_28G_LNaRGCR1_DATA_LOST_FLT BIT(30)
-#define LYNX_28G_LNaRGCR1_DATA_LOST BIT(29)
-#define LYNX_28G_LNaRGCR1_IDLE_CONFIG BIT(28)
-#define LYNX_28G_LNaRGCR1_ENTER_IDLE_FLT_SEL(x) (((x) << 24) &
GENMASK(26, 24))
-#define LYNX_28G_LNaRGCR1_ENTER_IDLE_FLT_SEL_X(x) (((x) & GENMASK(26, 24)) >>
24)
-#define LYNX_28G_LNaRGCR1_EXIT_IDLE_FLT_SEL(x) (((x) << 20) & GENMASK(22, 20))
-#define LYNX_28G_LNaRGCR1_EXIT_IDLE_FLT_SEL_X(x) (((x) & GENMASK(22,
20)) >> 20)
-#define LYNX_28G_LNaRGCR1_DATA_LOST_TH_SEL(x) (((x) << 16) & GENMASK(18, 16))
-#define LYNX_28G_LNaRGCR1_DATA_LOST_TH_SEL_X(x) (((x) & GENMASK(18,
16)) >> 16)
-#define LYNX_28G_LNaRGCR1_EXT_REC_CLK_SEL(x) (((x) << 8) & GENMASK(10, 8))
-#define LYNX_28G_LNaRGCR1_EXT_REC_CLK_SEL_X(x) (((x) & GENMASK(10, 8)) >> 8)
-#define LYNX_28G_LNaRGCR1_WAKE_TX_DIS BIT(5)
-#define LYNX_28G_LNaRGCR1_PHY_RDY BIT(4)
-#define LYNX_28G_LNaRGCR1_CHANGE_RX_CLK BIT(3)
-#define LYNX_28G_LNaRGCR1_PWR_MGT(x) ((x) & GENMASK(2, 0))
-
#define LYNX_28G_LNaRECR0(lane) (0x800 + (lane) * 0x100
+ 0x50)
#define LYNX_28G_LNaRECR0_EQ_GAINK2_HF_OV_EN BIT(31)
@@ -216,13 +185,6 @@
#define LYNX_28G_LNaRECR1(lane) (0x800 + (lane) * 0x100
+ 0x54)
-#define LYNX_28G_LNaRECR1_EQ_BLW_OV_EN BIT(31)
-#define LYNX_28G_LNaRECR1_EQ_BLW_OV(x) (((x) << 24) & GENMASK(28, 24))
-#define LYNX_28G_LNaRECR1_EQ_BLW_OV_X(x) (((x) & GENMASK(28, 24)) >> 24)
-#define LYNX_28G_LNaRECR1_EQ_OFFSET_OV_EN BIT(23)
-#define LYNX_28G_LNaRECR1_EQ_OFFSET_OV(x) (((x) << 16) & GENMASK(21, 16))
-#define LYNX_28G_LNaRECR1_EQ_OFFSET_OV_X(x) (((x) & GENMASK(21, 16)) >> 16)
-
#define LYNX_28G_LNaRECR1_EQ_BLW_OV_EN BIT(31)
#define LYNX_28G_LNaRECR1_EQ_BLW_OV(x) (((x) << 24) & GENMASK(28, 24))
#define LYNX_28G_LNaRECR1_EQ_BLW_OV_X(x) (((x) & GENMASK(28,
24)) >> 24)
@@ -271,34 +233,8 @@
#define LYNX_28G_LNaRECR4_EQ_BIN_DATA(x) ((x) &
LYNX_28G_LNaRECR4_EQ_BIN_DATA_MSK)
#define LYNX_28G_LNaRECR4_EQ_BIN_DATA_SGN BIT(8)
-#define LYNX_28G_LNaRECR2_EQ_OFFSET_RNG_DBL BIT(31)
-#define LYNX_28G_LNaRECR2_EQ_BOOST(x) (((x) << 28) & GENMASK(29, 28))
-#define LYNX_28G_LNaRECR2_EQ_BOOST_X(x) (((x) & GENMASK(29,
28)) >> 28)
-#define LYNX_28G_LNaRECR2_EQ_BLW_SEL(x) (((x) << 24) &
GENMASK(25, 24))
-#define LYNX_28G_LNaRECR2_EQ_BLW_SEL_X(x) (((x) & GENMASK(25, 24)) >> 24)
-#define LYNX_28G_LNaRECR2_EQ_ZERO(x) (((x) << 16) & GENMASK(17, 16))
-#define LYNX_28G_LNaRECR2_EQ_ZERO_X(x) (((x) & GENMASK(17, 16)) >> 16)
-#define LYNX_28G_LNaRECR2_EQ_IND(x) (((x) << 12) & GENMASK(13, 12))
-#define LYNX_28G_LNaRECR2_EQ_IND_X(x) (((x) & GENMASK(13, 12)) >> 12)
-#define LYNX_28G_LNaRECR2_EQ_BIN_DATA_AVG_TC(x) (((x) << 4) &
GENMASK(5, 4))
-#define LYNX_28G_LNaRECR2_EQ_BIN_DATA_AVG_TC_X(x) (((x) & GENMASK(5, 4)) >> 4)
-#define LYNX_28G_LNaRECR2_SPARE_IN(x) ((x) & GENMASK(1, 0))
-
#define LYNX_28G_LNaRCCR0(lane) (0x800 + (lane) * 0x100
+ 0x68)
-#define LYNX_28G_LNaRCCR0_CAL_EN BIT(31)
-#define LYNX_28G_LNaRCCR0_MEAS_EN BIT(30)
-#define LYNX_28G_LNaRCCR0_CAL_BIN_SEL BIT(28)
-#define LYNX_28G_LNaRCCR0_CAL_DC3_DIS BIT(27)
-#define LYNX_28G_LNaRCCR0_CAL_DC2_DIS BIT(26)
-#define LYNX_28G_LNaRCCR0_CAL_DC1_DIS BIT(25)
-#define LYNX_28G_LNaRCCR0_CAL_DC0_DIS BIT(24)
-#define LYNX_28G_LNaRCCR0_CAL_AC3_OV_EN BIT(15)
-#define LYNX_28G_LNaRCCR0_CAL_AC3_OV(x) (((x) << 8) &
GENMASK(11, 8))
-#define LYNX_28G_LNaRCCR0_CAL_AC3_OV_X(x) (((x) & GENMASK(11, 8)) >> 8)
-#define LYNX_28G_LNaRCCR0_CAL_AC2_OV_EN BIT(7)
-#define LYNX_28G_LNaRCCR0_CAL_AC2_OV(x) ((x) & GENMASK(3, 0))
-
#define LYNX_28G_LNaRCCR0_CAL_EN BIT(31)
#define LYNX_28G_LNaRCCR0_MEAS_EN BIT(30)
#define LYNX_28G_LNaRCCR0_CAL_BIN_SEL BIT(28)
@@ -332,36 +268,8 @@
#define LYNX_28G_LNaRSCCR0_SMP_AUTOZ_EG1R_X(x) (((x) & GENMASK(5, 4)) >> 4)
#define LYNX_28G_LNaRSCCR0_SMP_AUTOZ_EG1F(x) ((x) & GENMASK(1, 0))
-#define LYNX_28G_LNaRSCCR0_SMP_OFF_EN BIT(31)
-#define LYNX_28G_LNaRSCCR0_SMP_OFF_OV_EN BIT(30)
-#define LYNX_28G_LNaRSCCR0_SMP_MAN_OFF_EN BIT(29)
-#define LYNX_28G_LNaRSCCR0_SMP_OFF_RNG_OV_EN BIT(27)
-#define LYNX_28G_LNaRSCCR0_SMP_OFF_RNG_4X_OV BIT(25)
-#define LYNX_28G_LNaRSCCR0_SMP_OFF_RNG_2X_OV BIT(24)
-#define LYNX_28G_LNaRSCCR0_SMP_AUTOZ_PD BIT(23)
-#define LYNX_28G_LNaRSCCR0_SMP_AUTOZ_CTRL(x) (((x) << 16) & GENMASK(19, 16))
-#define LYNX_28G_LNaRSCCR0_SMP_AUTOZ_CTRL_X(x) (((x) & GENMASK(19, 16)) >> 16)
-#define LYNX_28G_LNaRSCCR0_SMP_AUTOZ_D1R(x) (((x) << 12) & GENMASK(13, 12))
-#define LYNX_28G_LNaRSCCR0_SMP_AUTOZ_D1R_X(x) (((x) & GENMASK(13, 12)) >> 12)
-#define LYNX_28G_LNaRSCCR0_SMP_AUTOZ_D1F(x) (((x) << 8) & GENMASK(9, 8))
-#define LYNX_28G_LNaRSCCR0_SMP_AUTOZ_D1F(x) (((x) << 8) & GENMASK(9, 8))
-#define LYNX_28G_LNaRSCCR0_SMP_AUTOZ_D1F_X(x) (((x) & GENMASK(9, 8)) >> 8)
-#define LYNX_28G_LNaRSCCR0_SMP_AUTOZ_EG1R(x) (((x) << 4) & GENMASK(5, 4))
-#define LYNX_28G_LNaRSCCR0_SMP_AUTOZ_EG1R_X(x) (((x) & GENMASK(5, 4)) >> 4)
-#define LYNX_28G_LNaRSCCR0_SMP_AUTOZ_EG1F(x) ((x) & GENMASK(1, 0))
-
#define LYNX_28G_LNaTTLCR0(lane) (0x800 + (lane) * 0x100 + 0x80)
-#define LYNX_28G_LNaTTLCR0_TTL_FLT_SEL(x) (((x) << 24) & GENMASK(29, 24))
-#define LYNX_28G_LNaTTLCR0_TTL_FLT_SEL_X(x) (((x) & GENMASK(29, 24)) >> 24)
-#define LYNX_28G_LNaTTLCR0_TTL_SLO_PM_BYP BIT(22)
-#define LYNX_28G_LNaTTLCR0_STALL_DET_DIS BIT(21)
-#define LYNX_28G_LNaTTLCR0_INACT_MON_DIS BIT(20)
-#define LYNX_28G_LNaTTLCR0_CDR_OV(x) (((x) << 16) & GENMASK(18, 16))
-#define LYNX_28G_LNaTTLCR0_CDR_OV_X(x) (((x) & GENMASK(18, 16)) >> 16)
-#define LYNX_28G_LNaTTLCR0_DATA_IN_SSC BIT(15)
-#define LYNX_28G_LNaTTLCR0_CDR_MIN_SMP_ON(x) ((x) & GENMASK(1, 0))
-
#define LYNX_28G_LNaTTLCR0_TTL_FLT_SEL(x) (((x) << 24) & GENMASK(29, 24))
#define LYNX_28G_LNaTTLCR0_TTL_FLT_SEL_X(x) (((x) & GENMASK(29, 24)) >> 24)
#define LYNX_28G_LNaTTLCR0_TTL_SLO_PM_BYP BIT(22)
@@ -458,12 +366,6 @@ enum lynx_28g_lane_mode {
LANE_MODE_MAX,
};
-enum lynx_28g_eq_type {
- EQ_TYPE_NO_EQ = 0,
- EQ_TYPE_2TAP = 1,
- EQ_TYPE_3TAP = 2,
-};
-
struct lynx_28g_priv;
struct lynx_28g_pll {
@@ -527,8 +429,6 @@ static void lynx_28g_rmw(struct lynx_28g_priv *priv,
unsigned long off,
ioread32((lane)->priv->base + LYNX_28G_##reg((lane)->id))
#define lynx_28g_lane_write(lane, reg, val) \
iowrite32(val, (lane)->priv->base + LYNX_28G_##reg((lane)->id))
-#define lynx_28g_lane_write(lane, reg, val) \
- iowrite32(val, (lane)->priv->base + LYNX_28G_##reg((lane)->id))
#define lynx_28g_pll_read(pll, reg) \
ioread32((pll)->priv->base + LYNX_28G_##reg((pll)->id))
@@ -788,7 +688,7 @@ static void lynx_28g_lane_set_1g(struct lynx_28g_lane *lane,
lynx_28g_lane_write(lane, LNaRSCCR0, 0);
}
-tatic void lynx_28g_lane_set_10g(struct lynx_28g_lane *lane,
+static void lynx_28g_lane_set_10g(struct lynx_28g_lane *lane,
enum lynx_28g_lane_mode lane_mode)
{
bool is_xfi = lane_mode != LANE_MODE_USXGMII;
@@ -1213,6 +1113,35 @@ static void lynx_28g_snapshot_gains_cb(struct phy *phy,
void *priv)
*(ctx->eq_offset) = LYNX_28G_LNaRECR4_EQ_OFFSET_STAT_X(recr4);
}
+static int lynx_28g_snapshot_rx_eq_gains(struct phy *phy, u8 *gaink2,
+ u8 *gaink3, u8 *eq_offset)
+{
+ struct lynx_28g_snapshot_gains_ctx ctx = {
+ .gaink2 = gaink2,
+ .gaink3 = gaink3,
+ .eq_offset = eq_offset,
+ };
+
+ return lynx_28g_snapshot_rx_eq(phy, EQ_BIN_DATA_SEL_BIN_1, &ctx,
+ lynx_28g_snapshot_gains_cb);
+}
+
+static void lynx_28g_snapshot_bin_cb(struct phy *phy, void *priv)
+{
+ struct lynx_28g_lane *lane = phy_get_drvdata(phy);
+ s16 *bin = priv;
+ int val;
+
+ /* The snapshot is a 2's complement 9 bit long value (-256 to 255) */
+ val = LYNX_28G_LNaRECR4_EQ_BIN_DATA(lynx_28g_lane_read(lane, LNaRECR4));
+ if (val & LYNX_28G_LNaRECR4_EQ_BIN_DATA_SGN) {
+ val &= ~LYNX_28G_LNaRECR4_EQ_BIN_DATA_SGN;
+ val -= 256;
+ }
+
+ *bin = (s16)val;
+}
+
static int lynx_28g_snapshot_rx_eq_bin(struct phy *phy, enum lynx_bin_type
bin_type,
s16 *bin)
{
@@ -1227,19 +1156,6 @@ static const struct lynx_xgkr_algorithm_ops
lynx_28g_xgkr_ops = {
.snapshot_rx_eq_bin = lynx_28g_snapshot_rx_eq_bin,
};
-static int lynx_28g_snapshot_rx_eq_gains(struct phy *phy, u8 *gaink2,
- u8 *gaink3, u8 *eq_offset)
-{
- struct lynx_28g_snapshot_gains_ctx ctx = {
- .gaink2 = gaink2,
- .gaink3 = gaink3,
- .eq_offset = eq_offset,
- };
-
- return lynx_28g_snapshot_rx_eq(phy, EQ_BIN_DATA_SEL_BIN_1, &ctx,
- lynx_28g_snapshot_gains_cb);
-}
-
static int lynx_28g_set_link_mode(struct phy *phy,
enum ethtool_link_mode_bit_indices submode)
{
@@ -1504,13 +1420,16 @@ static void lynx_28g_cdr_lock_check_work(struct
work_struct *work)
for (i = 0; i < LYNX_28G_NUM_LANE; i++) {
lane = &priv->lane[i];
- if (!lane->init)
- continue;
+ mutex_lock(&lane->phy->mutex);
- if (!lane->powered_up)
+ if (!lane->init || !lane->powered_up) {
+ mutex_unlock(&lane->phy->mutex);
continue;
+ }
lynx_28g_cdr_lock_check(lane);
+
+ mutex_unlock(&lane->phy->mutex);
}
queue_delayed_work(system_power_efficient_wq, &priv->cdr_check,
msecs_to_jiffies(1000));
@@ -1618,22 +1537,6 @@ static void lynx_28g_remove(struct platform_device *pdev)
cancel_delayed_work_sync(&priv->cdr_check);
}
-static void lynx_28g_remove(struct platform_device *pdev)
-{
- struct device *dev = &pdev->dev;
- struct lynx_28g_priv *priv = dev_get_drvdata(dev);
-
- cancel_delayed_work_sync(&priv->cdr_check);
-}
-
-static void lynx_28g_remove(struct platform_device *pdev)
-{
- struct device *dev = &pdev->dev;
- struct lynx_28g_priv *priv = dev_get_drvdata(dev);
-
- cancel_delayed_work_sync(&priv->cdr_check);
-}
-
static const struct of_device_id lynx_28g_of_match_table[] = {
{ .compatible = "fsl,lynx-28g" },
{ },
--
2.34.1
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