merged. Bruce
In message: [linux-yocto][v6.1/standard/nxp-sdk-6.1/nxp-soc & v6.1/standard/preempt-rt/nxp-sdk-6.1/nxp-soc][PATCH 1/3] phy: lynx-28g: truly power the lanes up or down on 16/04/2024 Xulin Sun wrote: > From: Vladimir Oltean <vladimir.olt...@nxp.com> > > commit f73df580c2379a90c9269dace6dc3084fdf85ccc from > https://github.com/nxp-imx/linux-imx lf-6.1.y > > The current procedure for power_off() and power_on() is the same as the > one used for major lane reconfiguration, aka halting. But one can > observe that a halted lane does not cause, for example, the CDR of the > link partner to lose lock. > > Implement the procedure mentioned in the block guide for powering down > a lane, and then back on. > > Signed-off-by: Vladimir Oltean <vladimir.olt...@nxp.com> > [Xulin: add functions lynx_28g_lane_halt() & lynx_28g_lane_reset() > directly, since they were mistakenly removed by the previous merge.] > Signed-off-by: Xulin Sun <xulin....@windriver.com> > --- > drivers/phy/freescale/phy-fsl-lynx-28g.c | 99 +++++++++++++++++++++++- > 1 file changed, 96 insertions(+), 3 deletions(-) > > diff --git a/drivers/phy/freescale/phy-fsl-lynx-28g.c > b/drivers/phy/freescale/phy-fsl-lynx-28g.c > index ccfdd36a89b7..5cb34312d593 100644 > --- a/drivers/phy/freescale/phy-fsl-lynx-28g.c > +++ b/drivers/phy/freescale/phy-fsl-lynx-28g.c > @@ -87,6 +87,8 @@ > > /* Lane a Tx Reset Control Register */ > #define LYNX_28G_LNaTRSTCTL(lane) (0x800 + (lane) * 0x100 + 0x20) > +#define LYNX_28G_LNaTRSTCTL_DIS BIT(24) > +#define LYNX_28G_LNaTRSTCTL_STP_REQ BIT(26) > #define LYNX_28G_LNaTRSTCTL_HLT_REQ BIT(27) > #define LYNX_28G_LNaTRSTCTL_RST_DONE BIT(30) > #define LYNX_28G_LNaTRSTCTL_RST_REQ BIT(31) > @@ -143,6 +145,8 @@ > > /* Lane a Rx Reset Control Register */ > #define LYNX_28G_LNaRRSTCTL(lane) (0x800 + (lane) * 0x100 + 0x40) > +#define LYNX_28G_LNaRRSTCTL_DIS BIT(24) > +#define LYNX_28G_LNaRRSTCTL_STP_REQ BIT(26) > #define LYNX_28G_LNaRRSTCTL_HLT_REQ BIT(27) > #define LYNX_28G_LNaRRSTCTL_RST_DONE BIT(30) > #define LYNX_28G_LNaRRSTCTL_RST_REQ BIT(31) > @@ -948,6 +952,95 @@ static void lynx_28g_lane_set_25g(struct lynx_28g_lane > *lane, > LYNX_28G_LNaTTLCR0_CDR_MIN_SMP_ON(1)); > } > > +/* Halting puts the lane in a mode in which it can be reconfigured */ > +static void lynx_28g_lane_halt(struct phy *phy) > +{ > + struct lynx_28g_lane *lane = phy_get_drvdata(phy); > + u32 trstctl, rrstctl; > + > + /* Issue a halt request */ > + lynx_28g_lane_rmw(lane, LNaTRSTCTL, LYNX_28G_LNaTRSTCTL_HLT_REQ, > + LYNX_28G_LNaTRSTCTL_HLT_REQ); > + lynx_28g_lane_rmw(lane, LNaRRSTCTL, LYNX_28G_LNaRRSTCTL_HLT_REQ, > + LYNX_28G_LNaRRSTCTL_HLT_REQ); > + > + /* Wait until the halting process is complete */ > + do { > + trstctl = lynx_28g_lane_read(lane, LNaTRSTCTL); > + rrstctl = lynx_28g_lane_read(lane, LNaRRSTCTL); > + } while ((trstctl & LYNX_28G_LNaTRSTCTL_HLT_REQ) || > + (rrstctl & LYNX_28G_LNaRRSTCTL_HLT_REQ)); > +} > + > +static void lynx_28g_lane_reset(struct phy *phy) > +{ > + struct lynx_28g_lane *lane = phy_get_drvdata(phy); > + u32 trstctl, rrstctl; > + > + /* Issue a reset request on the lane */ > + lynx_28g_lane_rmw(lane, LNaTRSTCTL, LYNX_28G_LNaTRSTCTL_RST_REQ, > + LYNX_28G_LNaTRSTCTL_RST_REQ); > + lynx_28g_lane_rmw(lane, LNaRRSTCTL, LYNX_28G_LNaRRSTCTL_RST_REQ, > + LYNX_28G_LNaRRSTCTL_RST_REQ); > + > + /* Wait until the reset sequence is completed */ > + do { > + trstctl = lynx_28g_lane_read(lane, LNaTRSTCTL); > + rrstctl = lynx_28g_lane_read(lane, LNaRRSTCTL); > + } while (!(trstctl & LYNX_28G_LNaTRSTCTL_RST_DONE) || > + !(rrstctl & LYNX_28G_LNaRRSTCTL_RST_DONE)); > +} > + > +static int lynx_28g_power_off(struct phy *phy) > +{ > + struct lynx_28g_lane *lane = phy_get_drvdata(phy); > + u32 trstctl, rrstctl; > + > + if (!lane->powered_up) > + return 0; > + > + /* Issue a stop request */ > + lynx_28g_lane_rmw(lane, LNaTRSTCTL, LYNX_28G_LNaTRSTCTL_STP_REQ, > + LYNX_28G_LNaTRSTCTL_STP_REQ); > + lynx_28g_lane_rmw(lane, LNaRRSTCTL, LYNX_28G_LNaRRSTCTL_STP_REQ, > + LYNX_28G_LNaRRSTCTL_STP_REQ); > + > + /* Wait until the stop process is complete */ > + do { > + trstctl = lynx_28g_lane_read(lane, LNaTRSTCTL); > + rrstctl = lynx_28g_lane_read(lane, LNaRRSTCTL); > + } while ((trstctl & LYNX_28G_LNaTRSTCTL_STP_REQ) || > + (rrstctl & LYNX_28G_LNaRRSTCTL_STP_REQ)); > + > + /* Power down the RX and TX portions of the lane */ > + lynx_28g_lane_rmw(lane, LNaRRSTCTL, LYNX_28G_LNaRRSTCTL_DIS, > + LYNX_28G_LNaRRSTCTL_DIS); > + lynx_28g_lane_rmw(lane, LNaTRSTCTL, LYNX_28G_LNaTRSTCTL_DIS, > + LYNX_28G_LNaTRSTCTL_DIS); > + > + lane->powered_up = false; > + > + return 0; > +} > + > +static int lynx_28g_power_on(struct phy *phy) > +{ > + struct lynx_28g_lane *lane = phy_get_drvdata(phy); > + > + if (lane->powered_up) > + return 0; > + > + /* Power up the RX and TX portions of the lane */ > + lynx_28g_lane_rmw(lane, LNaRRSTCTL, 0, LYNX_28G_LNaRRSTCTL_DIS); > + lynx_28g_lane_rmw(lane, LNaTRSTCTL, 0, LYNX_28G_LNaTRSTCTL_DIS); > + > + lynx_28g_lane_reset(phy); > + > + lane->powered_up = true; > + > + return 0; > +} > + > static int lynx_28g_set_lane_mode(struct phy *phy, enum lynx_28g_lane_mode > lane_mode) > { > struct lynx_28g_lane *lane = phy_get_drvdata(phy); > @@ -966,7 +1059,7 @@ static int lynx_28g_set_lane_mode(struct phy *phy, enum > lynx_28g_lane_mode lane_ > * the reconfiguration is being done. > */ > if (powered_up) > - lynx_28g_power_off(phy); > + lynx_28g_lane_halt(phy); > > spin_lock(&priv->pcc_lock); > > @@ -1001,9 +1094,9 @@ static int lynx_28g_set_lane_mode(struct phy *phy, enum > lynx_28g_lane_mode lane_ > out: > spin_unlock(&priv->pcc_lock); > > - /* Power up the lane if necessary */ > + /* Reset the lane if necessary */ > if (powered_up) > - lynx_28g_power_on(phy); > + lynx_28g_lane_reset(phy); > > return err; > } > -- > 2.34.1 >
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