Signed-off-by: Paul Butler <paul.but...@windriver.com>
---
arch/arm/boot/compressed/head.S | 63 ++--------
arch/arm/boot/dts/axm55xx.dts | 235 +++++++++++---------------------------
arch/arm/boot/emuboot/Makefile | 10 +-
arch/arm/boot/emuboot/emuboot.S | 27 ++++-
arch/arm/boot/emuboot/emuboot.lds | 4 +-
5 files changed, 109 insertions(+), 230 deletions(-)
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index f83c98c..001e661 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -171,7 +171,12 @@ not_angel:
@ determine final kernel image address
mov r4, pc
and r4, r4, #0xf8000000
+#ifdef CONFIG_ARCH_AXXIA
+ ldr r3, =TEXT_OFFSET
+ add r4, r4, r3
+#else
add r4, r4, #TEXT_OFFSET
+#endif
#else
ldr r4, =zreladdr
#endif
@@ -269,7 +274,12 @@ restart: adr r0, LC0
* of RAM and hope for the best.
*/
cmp r0, #1
+#ifdef CONFIG_ARCH_AXXIA
+ ldr r1, =TEXT_OFFSET
+ sub r0, r4, r1
+#else
sub r0, r4, #TEXT_OFFSET
+#endif
add r0, r0, #0x100
mov r1, r6
sub r2, sp, r6
@@ -567,58 +577,6 @@ __armv3_mpu_cache_on:
mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
mov pc, lr
-#if defined(CONFIG_ARCH_AXXIA)
-__setup_mmu:
- sub r3, r4, #16384 @ Page directory size
- bic r3, r3, #0xff @ Align the pointer
- bic r3, r3, #0x3f00
-
- /*
- * Clear the level 1 page table.
- */
-
- mov r0, #0
- mov r1, r3
- add r2, r3, #0x4000
-1: str r0, [r1], #4
- cmp r1, r2
- blt 1b
-
- /*
- * First 1G is RAM, cacheable and bufferable.
- */
-
- ldr r0, =0x40c1e
- mov r1, r3
- add r2, r3, #0x1000
-1: mov r9, #0
-2: str r0, [r1], #4 @ Each supersection is repeated
- add r9, r9, #1 @ 16 times.
- cmp r9, #16
- blt 2b
- add r0, r0, #0x1000000 @ 16M
- cmp r1, r2
- blt 1b
-
- /*
- * Third 1G is IO, not cacheable or bufferable.
- */
-
- ldr r0,=0x10040c52 @ Start at 0x20_1000_0000
- add r1, r3, #0x2000
- add r2, r3, #0x3000
-1: mov r9, #0
-2: str r0, [r1], #4 @ Each supersection is repeated
- add r9, r9, #1 @ 16 times.
- cmp r9, #16
- blt 2b
- add r0, r0, #0x1000000 @ 16M
- cmp r1, r2
- blt 1b
-
- mov pc, lr
-ENDPROC(__setup_mmu)
-#else
__setup_mmu: sub r3, r4, #16384 @ Page directory size
bic r3, r3, #0xff @ Align the pointer
bic r3, r3, #0x3f00
@@ -662,7 +620,6 @@ __setup_mmu: sub r3, r4, #16384 @ Page
directory size
str r1, [r0]
mov pc, lr
ENDPROC(__setup_mmu)
-#endif
__arm926ejs_mmu_cache_on:
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
diff --git a/arch/arm/boot/dts/axm55xx.dts b/arch/arm/boot/dts/axm55xx.dts
index f397394..ae94ca4 100644
--- a/arch/arm/boot/dts/axm55xx.dts
+++ b/arch/arm/boot/dts/axm55xx.dts
@@ -30,8 +30,9 @@
chosen { };
aliases {
- serial0 = &axxia_serial0;
- timer = &axxia_timers;
+ serial0 = &axxia_serial0;
+ timer = &axxia_timers;
+ ethernet0 = &axxia_femac0;
};
cpus {
@@ -42,12 +43,57 @@
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0>;
+ cpu-release-addr = <0>; // Fixed by the boot loader
};
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <1>;
+ cpu-release-addr = <0>; // Fixed by the boot loader
+ };
+
+ cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <2>;
+ cpu-release-addr = <0>; // Fixed by the boot loader
+ };
+
+ cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <3>;
+ cpu-release-addr = <0>; // Fixed by the boot loader
+ };
+
+ /*
+ cpu@4 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <4>;
+ cpu-release-addr = <0>; // Fixed by the boot loader
+ };
+
+ cpu@5 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <5>;
+ cpu-release-addr = <0>; // Fixed by the boot loader
+ };
+
+ cpu@6 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <6>;
+ cpu-release-addr = <0>; // Fixed by the boot loader
+ };
+ */
};
memory@00000000 {
device_type = "memory";
- reg = <0 0x00000000 0 0x40000000>;
+ reg = <0 0x00000000 0 0x10000000>;
};
gic: interrupt-controller@2001001000 {
@@ -55,8 +101,10 @@
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
- reg = <0x20 0x01001000 0 0x1000>,
- <0x20 0x01002000 0 0x100>;
+ reg = <0x20 0x01001000 0 0x1000>, /* gic dist base */
+ <0x20 0x01002000 0 0x100>, /* gic cpu base */
+ <0x20 0x10030000 0 0x100>, /* axm IPI mask reg base */
+ <0x20 0x10040000 0 0x20000>; /* axm IPI send reg base */
};
timer {
@@ -102,21 +150,20 @@
reg = <0x20 0x10094000 0 0x1000>;
};
- mtc@2010098000 {
- compatible = "lsi,mtc";
- reg = <0x20 0x10098000 0 0x3000>;
- interrupts = <0 45 4>;
- };
-
- ethernet@201100000000 {
- compatible = "smsc,lan91c111";
+ axxia_femac0: femac@0x2010120000 {
+ compatible = "acp-femac";
device_type = "network";
- reg = <0x20 0x11000000 0 0x10000>;
- interrupts = <0 1 4>;
- phy-mode = "mii";
- reg-io-width = <4>;
- smsc,irq-active-high;
- smsc,irq-push-pull;
+ reg = <0x20 0x10120000 0 0x1000>,
+ <0x20 0x10121000 0 0x1000>,
+ <0x20 0x10122000 0 0x1000>;
+ interrupts = <0 2 4>,
+ <0 3 4>,
+ <0 4 4>;
+ mdio-reg = <0x20 0x10090000 0 0x1000>;
+ mdio-clock = <0>;
+ phy-address = <0x3>;
+ ad-value = <0x61>;
+ mac-address = [00 00 00 00 00 00];
};
amba {
@@ -125,13 +172,6 @@
#size-cells = <2>;
ranges;
- mmci@020101E0000 {
- compatible = "arm,pl180", "arm,primecell";
- reg = <0x20 0x101E0000 0x00 0x1000>;
- interrupts = <0 222 4>,
- <0 223 4>;
- };
-
axxia_serial0: uart@2010080000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x20 0x10080000 0x00 0x1000>;
@@ -141,153 +181,16 @@
axxia_timers: timer@2010091000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x20 0x10091000 0 0x1000>;
- interrupts = <0 47 4>,
+ interrupts = <0 46 4>,
+ <0 47 4>,
<0 48 4>,
<0 49 4>,
<0 50 4>,
<0 51 4>,
<0 52 4>,
- <0 53 4>,
- <0 54 4>;
+ <0 53 4>;
};
-
- gpio@2010092000 {
- compatible = "arm,pl061", "arm,primecell";
- reg = <0x20 0x10092000 0 0x1000>;
- interrupts = <0 10 4>,
- <0 11 4>,
- <0 12 4>,
- <0 13 4>,
- <0 14 4>,
- <0 15 4>,
- <0 16 4>,
- <0 17 4>;
- };
-
- gpio@2010093000 {
- compatible = "arm,pl061", "arm,primecell";
- reg = <0x20 0x10093000 0x00 0x1000>;
- interrupts = <0 18 4>;
- };
-
- ssp@2010088000 {
- compatible = "arm,pl022", "arm,primecell";
- reg = <0x20 0x10088000 0x00 0x1000>;
- interrupts = <0 42 4>;
- };
-
};
-
- PCIE0: pciex@0xf0120000 {
- compatible = "lsi,plb-pciex";
- device_type = "pci";
- status = "ok";
- port = <0>;
- #interrupt-cells = <1>;
- #size-cells = <2>;
- #address-cells = <3>;
- /* config space access MPAGE7 registers*/
- reg = < 0x30 0x38000000 0x0 0x01000000
- 0x20 0x20120000 0x0 0x00008000 >;
- /* Outbound ranges */
- /* < <3-cell PCI addr> <2-cell CPU (PLB) addr> <2-cell size> >
*
-/
- ranges = <0x03000000 0x00000000 0xa0000000
- 0x30 0x00000000
- 0x00 0x20000000>;
- /* Inbound ranges */
- /* < <3-cell PCI addr> <2-cell CPU addr> <2-cell size> > */
- dma-ranges = <0x03000000 0x00000000 0x00000000
- 0x00 0x00000000
- 0x00 0x40000000>;
- interrupts = <0 68 4>,
- <0 73 4>,
- <0 74 4>,
- <0 75 4>,
- <0 76 4>,
- <0 77 4>,
- <0 78 4>,
- <0 79 4>,
- <0 80 4>,
- <0 81 4>,
- <0 82 4>,
- <0 83 4>,
- <0 84 4>,
- <0 85 4>,
- <0 86 4>,
- <0 87 4>,
- <0 88 4>;
-
- };
-
- PCIE1: pciex@0xf0128000 {
- compatible = "lsi,plb-pciex";
- device_type = "pci";
- status = "ok";
- port = <1>;
- #interrupt-cells = <1>;
- #size-cells = <2>;
- #address-cells = <3>;
-
- /* config space access MPAGE7 registers*/
- reg = <0x30 0xb8000000 0x0 0x01000000
- 0x20 0x20130000 0x0 0x00008000 >;
- /* Outbound ranges */
- /* < <3-cell PCI addr> <2-cell CPU (PLB) addr> <2-cell size> >
*/
- ranges = <0x03000000 0x00000000 0xa0000000
- 0x30 0x80000000
- 0x00 0x20000000>;
- /* Inbound ranges */
- /* < <3-cell PCI addr> <2-cell CPU addr> <2-cell size> > */
- dma-ranges = <0x03000000 0x00000000 0x00000000
- 0x00 0x00000000
- 0x00 0x40000000>;
- interrupts = <0 70 4>;
- };
-
- I2C0: i2c@0x02010084000 {
- compatible = "lsi,api2c";
- device_type = "i2c";
- enabled = <0>;
- port = <0>;
- /* bus_name = "auto"; */
- /* bus = <2>; */
- reg = <0x20 0x10084000 0x00 0x1000>;
- interrupts = <0 19 4>;
- };
-
- I2C1: i2c@0x02010085000 {
- compatible = "lsi,api2c";
- device_type = "i2c";
- enabled = <0>;
- port = <1>;
- /* bus_name = "auto"; */
- /* bus = <3>; */
- reg = <0x20 0x10085000 0x00 0x1000>;
- interrupts = <0 20 4>;
- };
-
- I2C2: i2c@0x02010086000 {
- compatible = "lsi,api2c";
- device_type = "i2c";
- enabled = <0>;
- port = <2>;
- /* bus_name = "auto"; */
- /* bus = <4>; */
- reg = <0x20 0x10086000 0x00 0x1000>;
- interrupts = <0 21 4>;
- };
-
- SMB: i2c@0x02010087000 {
- compatible = "lsi,api2c";
- device_type = "i2c";
- enabled = <0>;
- port = <3>;
- bus_name = "smb";
- /* bus = <5>; */
- reg = <0x20 0x10087000 0x00 0x1000>;
- interrupts = <0 22 4>;
- };
};
/*
diff --git a/arch/arm/boot/emuboot/Makefile b/arch/arm/boot/emuboot/Makefile
index eb907c5..3fdecdd 100644
--- a/arch/arm/boot/emuboot/Makefile
+++ b/arch/arm/boot/emuboot/Makefile
@@ -6,20 +6,20 @@ OBJCOPY = $(CROSS_COMPILE)objcopy
DTC = ../../../../scripts/dtc/dtc
DTS = ../dts/axm55xx.dts
-ZIMAGE = ../zImage
+IMAGE = ../zImage
all: clean linux.img
clean:
- rm -f linux.img emuboot.o zImage.emu axm55xx.dtb
+ rm -f linux.img emuboot.o image.emu axm55xx.dtb
-linux.img: emuboot.o emuboot.lds zImage.emu
+linux.img: emuboot.o emuboot.lds image.emu
$(LD) -o linux.tmp --script=emuboot.lds
$(OBJCOPY) -O binary -R .note -R .comment -S linux.tmp $@
rm -f linux.tmp
-zImage.emu: $(ZIMAGE) axm55xx.dtb
- python pack.py $(ZIMAGE) axm55xx.dtb > $@
+image.emu: $(ZIMAGE) axm55xx.dtb
+ python pack.py $(IMAGE) axm55xx.dtb > $@
axm55xx.dtb: $(DTS)
$(DTC) -O dtb -o $@ $<
diff --git a/arch/arm/boot/emuboot/emuboot.S b/arch/arm/boot/emuboot/emuboot.S
index a39945a..45bb607 100644
--- a/arch/arm/boot/emuboot/emuboot.S
+++ b/arch/arm/boot/emuboot/emuboot.S
@@ -45,14 +45,32 @@ _start:
lsr r0, r0, #16
ands r0, r0, #1 @ Check generic timer support
beq 1f
- ldr r0, =6250000 @ 6.25 MHz timer frequency
+ @ldr r0, =6250000 @ 6.25 MHz timer frequency
+ ldr r0, =4096000 @ 4.096 MHz timer frequency
mcr p15, 0, r0, c14, c0, 0 @ CNTFRQ
-1:
@
+ @ CPU initialisation
+ @
+1: mrc p15, 0, r0, c0, c0, 5 @ MPIDR (ARMv7 only)
+ mov r1, r0
+ and r0, r1,0x3 @ CPU number
+ cmp r0, #0 @ primary CPU in any cluster
+ bne actlr2_set
+ lsr r0, r1, #8
+ ands r0, r0, #3 @ primary CPU in cluster 0
+ beq primary
+
+ @
+ @ Secondary CPUs
+ @
@ Set the L2ACTLR
@
- mrc p15, 1, r0, c15, c0, 0 @ L2ACTLR
+secondary: and r1, r1,0x3 @ CPU number
+ cmp r1, #0
+ bne actlr2_set
+
+ mrc p15, 1, r0, c15, c0, 0 @ L2ACTLR
@ Set bit 3 - disable clean/evict push to external
orr r0, r0, #(0x1 << 3)
@ Set bit 12 - disable multiple outstanding
@@ -118,9 +136,10 @@ atags:
@ ATAG_CMDLINE
.long (1f - .) >> 2
.long 0x54410009
- .asciz "root=/dev/mmcblk0 rootwait ip=none mem=1024M console=ttyAMA0
earlyprintk"
+ .asciz "root=/dev/nfs rw mem=1024M console=ttyAMA0 ip=dhcp"
.align 2
+
1:
@ ATAG_NONE
diff --git a/arch/arm/boot/emuboot/emuboot.lds
b/arch/arm/boot/emuboot/emuboot.lds
index 0a24a17..38df9cd 100644
--- a/arch/arm/boot/emuboot/emuboot.lds
+++ b/arch/arm/boot/emuboot/emuboot.lds
@@ -12,7 +12,7 @@ OUTPUT_ARCH(arm)
TARGET(binary)
INPUT(./emuboot.o)
-INPUT(./zImage.emu)
+INPUT(./image.emu)
PHYS_OFFSET = 0x00000000;
@@ -22,7 +22,7 @@ SECTIONS
.text : { emuboot.o }
. = PHYS_OFFSET + 0x8000 - 0x0;
kernel = . + 0x0;
- .kernel : { ./zImage.emu }
+ .kernel : { ./image.emu }
. = PHYS_OFFSET + 0x00800000;
filesystem = .;
.data : { *(.data) }
--
1.8.3.4
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