Actually,
Previously I moved most of the boot scripts off to a backup directory...
There was really no change. I have since moved all boot scripts to a
directory called "/etc/rc.d/HOLD". Heh... This was kind of a mistake.
For those interested, I have attached a copy of my serial post to this
message. I'm probably going to re-build from scratch soon since I have
been doing a lot of un-organized development on this system.
BTW, it seems that there is no booting action (Based on the Serial
output) until the HDD spins up. Is this a result of me keeping my root
file system on the HDD?
Regards,
Todd E. Johnson
[EMAIL PROTECTED]
> -----Original Message-----
> From: Gregg C Levine [mailto:[EMAIL PROTECTED]]
> Sent: Friday, October 04, 2002 10:17 PM
> To: [EMAIL PROTECTED]; 'Ronald G Minnich'
> Cc: [EMAIL PROTECTED]
> Subject: RE: PCChips M758LMR+ works for me but...
>
>
> Hello from Gregg C Levine
> Um, Todd, way to go choosing Slackware, that's what I use. Now what's
> this about the slowness of the bootup scripts? I use Slackware here,
> and about all I can say, it's a bit strange about those scripts. Of
> course, this is version, 8.0, I haven't ordered copies of 8.1
> on CD yet.
> -------------------
> Gregg C Levine [EMAIL PROTECTED]
> ------------------------------------------------------------
> "The Force will be with you...Always." Obi-Wan Kenobi
> "Use the Force, Luke."� Obi-Wan Kenobi
> (This company dedicates this E-Mail to General Obi-Wan Kenobi )
> (This company dedicates this E-Mail to Master Yoda )
>
>
LinuxBIOS-1.0.0 Fri Oct 4 10:34:57 EST 2002 starting...
Copying LinuxBIOS to ram.
POST: 0x39, TSC Lo: 1019, Hi: 2563
LinuxBIOS-1.0.0 Fri Oct 4 10:34:57 EST 2002 booting...
POST: 0x40, TSC Lo: 44466, Hi: 55
Finding PCI configuration type.
PCI: Using configuration type 1
POST: 0x5f, TSC Lo: 50336, Hi: 50208
handle_superio start, s 0000d140 nsuperio 1 s->super 0000e498
handle_superio Pass 0, check #0, s 0000d140 s->super 0000e498
handle_superio: Pass 0, Superio SiS 950
handle_superio port 0x0, defaultp
handle_superio Using port 0x2e
handle_superio Pass 0, done #0
handle_superio done
Scanning PCI bus...PCI: pci_scan_bus for bus 0
POST: 0x24, TSC Lo: 59844, Hi: 0
PCI: 00:00.0 [1039/0630]
PCI: 00:00.1 [1039/5513]
PCI: 00:01.0 [1039/0008]
PCI: 00:01.4 [1039/7018]
PCI: 00:02.0 [1039/0001]
PCI: 00:0b.0 [3388/0021]
PCI: 00:0d.0 [109e/036e]
PCI: 00:0d.1 [109e/0878]
PCI: 00:0f.0 [13f6/0111]
POST: 0x25, TSC Lo: -1, Hi: -1
PCI: pci_scan_bus for bus 1
POST: 0x24, TSC Lo: 77248, Hi: 0
PCI: 01:00.0 [1039/6300]
POST: 0x25, TSC
PCI: pci_scan_bus returning with max=01
POST: 0x55, TSC Lo: 50186, Hi: 40
PCI: pci_scan_bus for bus 2
POST: 0x24, TSC Lo: 77452, Hi: 0
PCI: 02:08.0 [1033/0035]
PCI: 02:08.1 [1033/0035]
PCI: 02:08.2 [1033/00e0]
PCI: 02:0b.0 [104c/8020]
POST: 0x25, TSC Lo: -1, Hi: -1
PCI: pci_scan_bus returning with max=02
POST: 0x55, TSC Lo: 50186, Hi: 40
PCI: pci_scan_bus returning with max=02
POST: 0x55, TSC Lo: 50186, Hi: 40
done
POST: 0x66, TSC Lo: 50522, Hi: 5
POST: 0x70, TSC Lo: 2, Hi: 58720
totalram: 504M
Initializing CPU #0
Updating microcode
microcode_info: sig = 0x000006b1 pf=0x00000010 rev = 0x00000000
POST: 0x60, TSC Lo: 47924, Hi: 64
Enabling cache...
Setting fixed MTRRs(0-88) type: UC
Setting fixed MTRRs(0-16) type: WB
DONE fixed MTRRs
Setting variable MTRR 0, base: 0MB, range: 256MB, type WB
Setting variable MTRR 1, base: 256MB, range: 128MB, type WB
Setting variable MTRR 2, base: 384MB, range: 64MB, type WB
Setting variable MTRR 3, base: 448MB, range: 32MB, type WB
Setting variable MTRR 4, base: 480MB, range:
Setting variable MTRR 5, base: 496MB, range: 8MB, type WB
DONE variable MTRRs
Clear out the extra MTRR's
call intel_enable_fixed_mtrr()
call intel_enable_var_mtrr()
Leave setup_mtrrs
POST: 0x6a, TSC Lo: 53043, Hi: 18
done.
Max cpuid index : 2
Vendor ID : GenuineIntel
Processor Type : 0x00
Processor Family : 0x06
Processor Model : 0x0b
Processor Mask : 0x00
Processor Stepping : 0x01
Feature flags : 0x0383fbff
Cache/TLB descriptor values: 1 reads required
Desc 0x01 : Instr TLB: 4KB pages, 4-way set assoc, 32 entries
Desc 0x02 : Instr TLB: 4MB pages, fully assoc, 2 entries
Desc 0x03 : Data TLB: 4KB pages, 4-way set assoc, 64 entries
Desc 0x00 : null
Desc 0x00 : null
Desc 0x00 : null
Desc 0x00 : null
Desc 0x00 : null
Desc 0x00 : null
Desc 0x00 : null
Desc 0x00 : null
Desc 0x82 : L2 Unified cache: 256K bytes, 8-way set assoc, 32 byte line size
Desc 0x08 : Inst cache: 16K bytes, 4-way set assoc, 32 byte line size
Desc 0x04 : Data TLB: 4MB pages, 4-way set assoc, 8 entr
Desc 0x0c : Data cache: 16K bytes, 2-way or 4-way set assoc, 32 byte line size
POST: 0x92, TSC Lo: 45859, Hi: 1
MTRR check
Fixed MTRRs : Enabled
Variable MTRRs: Enabled
POST: 0x93, TSC Lo: 45859, Hi: 1
Configuring L2 cache...CPU signature of 6b0 so no L2 cache configuration
Enable Cache
done.
Disabling local apic...done.
POST: 0x9b, TSC Lo: 52649, Hi: 6
CPU #0 Initialized
POST: 0x75, TSC Lo: 44394, Hi: 0
POST: 0x77, TSC Lo: 43649, Hi: 117
Allocating PCI resources...
PCI: 00:0f.0 register 10(0000ff01), read-only
PCI: 00:0f.0 register 10(0000ff01), read-only ignoring it
PCI: 00:0f.0 register 10(0000ff01), read-only ignoring it
PCI: 00:0f.0 register 10(0000ff01), read-only ignoring it
ASSIGN RESOURCES, bus 0
PCI: 00:00.0 10 <- [0xf8000000 - 0xfbffffff] mem
PCI: 00:00.1 10 <- [0x00002410 - 0x00002417] io
PCI: 00:00.1 14 <- [0x00002430 - 0x00002433] io
PCI: 00:00.1 18 <- [0x00002420 - 0x00002427] io
PCI: 00:00.1 1c <- [0x00002440 - 0x00002443] io
PCI: 00:00.1 20 <- [0x00002400 - 0x0000240f] io
PCI: 00:01.4 10 <- [0x00002000
PCI: 00:01.4 14 <- [0xfc200000 - 0xfc200fff] mem
PCI: 00:02.0 1c <- [0x00001000 - 0x00001fff] bus 1 @)io
PCI: 00:02.0 24 <- [0xf0000000 - 0xf7ffffff] bus 1 @)prefmem
PCI: 00:02.0 20 <- [0xfc000000 - 0xfc0fffff] bus 1 @)mem
ASSIGN RESOURCES, bus 1
PCI: 01:00.0 10 <- [0xf0000000 - 0xf7ffffff] prefmem
PCI: 01:00.0 14 <- [0xfc000000 - 0xfc01ffff] mem
PCI: 01:00.0 18 <- [0x00001000 - 0x0000107f] io
PCI: 00:0b.0 1c <- [0x00002000 - 0x00001fff] bus 2 @)io
PCI: 00:0b.0 24 <- [0xfc200000 - 0xfc1ff
PCI: 00:0b.0 20 <- [0xfc100000 - 0xfc1fffff] bus 2 @)mem
ASSIGN RESOURCES, bus 2
PCI: 02:08.0 10 <- [0xfc104000 - 0xfc104fff] mem
PCI: 02:08.1 10 <- [0xfc105000 - 0xfc105fff] mem
PCI: 02:08.2 10 <- [0xfc107000 - 0xfc1070ff] mem
PCI: 02:0b.0 10 <- [0xfc106000 - 0xfc1067ff] mem
PCI: 02:0b.0 14 <- [0xfc100000 - 0xfc103fff] mem
PCI: 00:0d.0 10 <- [0xfc201000 - 0xfc201fff] prefmem
PCI: 00:0d.1 10 <- [0xfc202000 - 0xfc202fff] prefmem
Allocating VGA resource
done.
POST: 0x88, TSC Lo: 50559, Hi: 6
Enabling PCI resourcess...PCI: 00:00.0 cmd <- 07
PCI: 00:00.1 cmd <- 01
PCI: 00:01.0 cmd <- 0c
PCI: 00:01.4 cmd <- 03
PCI: 00:02.0 cmd <- 27
PCI: 00:0b.0 cmd <- 07
PCI: 00:0d.0 cmd <- 02
PCI: 00:0d.1 cmd <- 02
PCI: 00:0f.0 cmd <- 80
PCI: 01:00.0 cmd <- 03
PCI: 02:08.0 cmd <- 02
PCI: 02:08.1 cmd <- 02
PCI: 02:08.2 cmd <- 02
PCI: 02:0b.0 cmd <- 02
done.
Initializing PCI devices...
PCI devices initialized
POST: 0x89, TSC Lo: 50666, Hi: 24
POST: 0x91, TSC Lo: 43649, Hi: 137
POST: 0x92, TSC Lo: 43649, Hi: 145
Enabled in SIS 503 regs 0x40 and 0x45
Now try to turn off shadow
device for SiS 630 is 0x12a8c
Shadow memory disabled in SiS 630
POST: 0x00, TSC Lo: 3327, Hi: 26
POST: 0x04, TSC Lo: 43649, Hi: 18
POST: 0x06, TSC Lo: 43649, Hi: 16
POST: 0x06, TSC Lo: 43649, Hi: 16
POST: 0x06, TSC Lo: 43649, Hi: 16
POST: 0x06, TSC Lo: 43649, Hi: 16
POST: 0x06, TSC Lo: 43649, Hi: 16
POST: 0x06, TSC Lo: 43649, Hi: 16
POST: 0x06, TSC Lo: 43649, Hi: 16
POST: 0x06, TSC Lo: 43649, Hi: 16
POST: 0x06, TSC Lo: 43649, Hi: 16
POST: 0x06, TSC Lo
POST: 0x06, TSC Lo: 43649, Hi: 16
POST: 0x06, TSC Lo: 43649, Hi: 16
POST: 0x06, TSC Lo: 43649, Hi: 16
POST: 0x06, TSC Lo: 43649, Hi: 16
POST: 0x06, TSC Lo: 43649, Hi: 16
POST: 0x06, TSC Lo: 43649, Hi: 16
POST: 0x06, TSC Lo: 43649, Hi: 16
POST: 0x06, TSC Lo: 43649, Hi: 16
POST: 0x06, TSC Lo: 43649, Hi: 16
POST: 0x06, TSC Lo: 43649, Hi: 16
POST: 0x06, TSC Lo: 43649, Hi: 16
POST: 0x06, TSC Lo: 43649, Hi: 16
POST: 0x06, TSC Lo: 43649, Hi: 16
POST: 0x06, TSC Lo: 43649, Hi: 16
POST: 0x06, TSC Lo: 43649, Hi: 16
POST: 0x06, TSC Lo: 43649, Hi: 16
POST: 0x06, TSC Lo: 43649, Hi: 16
POST: 0x06, TSC Lo: 43649, Hi: 16
POST: 0x06, TSC Lo: 43649, Hi: 16
POST: 0x06, TSC Lo: 43649, Hi: 16
POST: 0x06, TSC Lo: 43649, Hi: 16
POST: 0x06, TSC Lo: 43649, Hi: 16
POST: 0x06, TSC Lo: 43649, Hi: 16
POST: 0x06, TSC Lo: 43649, Hi: 16
POST: 0x06, TSC Lo: 43649, Hi: 16
POST: 0x06, TSC Lo: 43649, Hi: 16
POST: 0x06, TSC Lo: 43649, Hi: 16
POST: 0x06, TSC Lo: 43649, Hi: 16
POST: 0x06, TSC Lo: 43649, Hi: 16
POST: 0x06, TSC Lo: 43649, Hi: 16
POST: 0x06, TSC Lo: 43649, Hi: 16
POST: 0x06, TSC Lo: 43649, Hi: 16
POST: 0x06, TSC Lo: 43649, Hi: 16
POST: 0x06, TSC Lo: 43649, Hi: 16
POST: 0x06, TSC Lo: 43649, Hi: 16
POST: 0x06, TSC Lo: 43649, Hi: 16
POST: 0x06, TSC Lo: 43649, Hi: 16
POST: 0x06, TSC Lo: 43649, Hi: 16
POST: 0x06, TSC Lo: 43649, Hi: 16
POST: 0x06, TSC Lo: 43649, Hi: 16
POST: 0x06, TSC Lo: 43649, Hi: 16
POST: 0x06, TSC Lo: 43649, Hi: 16
POST: 0x06, TSC Lo: 43649, Hi: 16
POST: 0x06, TSC Lo: 43649, Hi: 16
POST: 0x06, TSC Lo: 43649, Hi: 16
POST: 0x06, TSC Lo: 43649, Hi: 16
POST: 0x06, TSC Lo: 43649, Hi: 16
POST: 0x06, TSC Lo: 43649, Hi: 16
POST: 0x06, TSC Lo: 43649, Hi: 16
POST: 0x06, TSC Lo: 43649, Hi: 16
POST: 0x06, TSC Lo: 43649, Hi: 16
POST: 0x06, TSC Lo: 43649, Hi: 16
POST: 0x06, TSC Lo: 43649, Hi: 16
POST: 0x06, TSC Lo: 43649, Hi: 16
POST: 0x06, TSC Lo: 43649, Hi: 16
POST: 0x06, TSC Lo: 43649, Hi: 16
POST: 0x06, TSC Lo: 43649, Hi: 16
POST: 0x06, TSC Lo: 43649, Hi: 16
POST: 0x06, TSC Lo: 43649, Hi: 16
POST: 0x06, TSC Lo: 43649, Hi: 16
POST: 0x06, TSC Lo: 43649, Hi: 16
POST: 0x06, TSC Lo: 43649, Hi: 16
POST: 0x06, TSC Lo: 43649, Hi: 16
POST: 0x06, TSC Lo: 43649, Hi: 16
POST: 0x06, TSC Lo: 43649, Hi: 16
POST: 0x06, TSC Lo: 43649, Hi: 16
POST: 0x06, TSC Lo: 43649, Hi: 16
POST: 0x06, TSC Lo: 43649, Hi: 16
POST: 0x06, TSC Lo: 43649, Hi: 16
handle_superio start, s 0000d140 nsuperio 1 s->super 0000e498
handle_superio Pass 1, check #0, s 0000d140 s->super 0000e498
handle_superio: Pass 1, Superio SiS 950
handle_superio port 0x2e, defaultport 0x2e
handle_superio Using port 0x2e
handle_superio Pass 1, done #0
handle_superio done
PCCHIPS m758lmr+ (and similar)...Entering the initregs process
Southbridge fixup done for SIS 503
POST: 0xec, TSC Lo: 45507, Hi: 35
handle_superio start, s 0000d140 nsuperio 1 s->super 0000e498
handle_superio Pass 2, check #0, s 0000d140 s->super 0000e498
handle_superio: Pass 2, Superio SiS 950
handle_superio port 0x2e, defaultport 0x2e
handle_superio Using port 0x2e
Call finishup
handle_superio Pass 2, done #0
handle_superio do
POST: 0x9a, TSC Lo: 51190, Hi: 20
Checking IRQ routing tables.../usr/local/src/freebios/src/arch/i386/lib/pirq_rou
ting.c: 24:check_pirq_routing_table() - irq_routing_table located at: 0x0000b
260
done.
Copying IRQ routing tables to 0xf0000...done.
POST: 0x96, TSC Lo: 44953, Hi: 983152
Wrote linuxbios table at: 00000500 - 0000065c checksum 9ed7
Jumping to linuxbiosmain()...
POST: 0xed, TSC Lo: 44574, Hi: 30
Welcome to start32, the open sourced starter.
This space will eventually hold more diagnostic informat
January 2000, James Hendricks, Dale Webster, and Ron Minnich.
Version 0.1
POST: 0xf1, TSC Lo: 49057, Hi: 1
init_bytes
Gunzip setup
gunzip_setup
output data is 0x00100000
Gunzipping boot code
43:fill_inbuf() - ram buffer:0x0001b5b4
done memcpy_from_doc_mil
53:fill_inbuf() - nvram:0x00010000 block_count:0
POST: 0xd0, TSC Lo: 43526, Hi: 208
inbuf[0] is 0x1f
flush 0x00100000 count 0x00008000
flush 0x00108000 count 0x00008000
flush 0x00110000 count 0x00008000
flush 0x00118000 count 0x00008000
done memcpy_from_d
53:fill_inbuf() - nvram:0x00020000 block_count:1
POST: 0xd1, TSC Lo: 43526, Hi: 209
inbuf[0] is 0x8c
flush 0x00120000 count 0x00008000
flush 0x00128000 count 0x00008000
flush 0x00130000 count 0x00008000
done memcpy_from_doc_mil
53:fill_inbuf() - nvram:0x00030000 block_count:2
POST: 0xd2, TSC Lo: 43526, Hi: 210
inbuf[0] is 0x9e
flush 0x00138000 count 0x00008000
flush 0x00140000 count 0x00008000
flush 0x00148000 count 0x00008000
flush 0x00150000 count 0x00008000
done memcpy_from_doc_mil
53:fill_inbuf() - nvram:0x00040000 block_count:3
POST: 0xd3, TSC Lo: 43526, Hi: 211
inbuf[0] is 0xf8
flush 0x00158000 count 0x00008000
flush 0x00160000 count 0x00008000
flush 0x00168000 count 0x00008000
done memcpy_from_doc_mil
53:fill_inbuf() - nvram:0x00050000 block_count:4
POST: 0xd4, TSC Lo: 43526, Hi: 212
inbuf[0] is 0xb7
flush 0x00170000 count 0x00008000
flush 0x00178000 count 0x00008000
flush 0x00180000 count 0x00008000
flush 0x00188000 count 0x00008000
done memcpy_from_doc_mil
53:fill_inbuf() - nvram:0x00060000 block_count:5
POST: 0xd5, TSC Lo: 43526, Hi: 213
inbuf[0] is 0xe4
flush 0x00190000 count 0x00008000
flush 0x00198000 count 0x00008000
flush 0x001a0000 count 0x00008000
flush 0x001a8000 count 0x00008000
done memcpy_from_doc_mil
53:fill_inbuf() - nvram:0x00070000 block_count:6
POST: 0xd6, TSC Lo: 43526, Hi: 214
inbuf[0] is 0x38
flush 0x001b0000 count 0x00008000
flush 0x001b8000 count 0x00008000
flush 0x001c0000 count 0x00008000
done memcpy_from_doc_mil
53:fill_inbuf() - nvram:0x00080000 block_count:7
POST: 0xd7, TSC Lo: 43526, Hi: 215
inbuf[0] is 0xf4
flush 0x001c8000 count 0x00008000
flush 0x001d0000 count 0x00008000
flush 0x001d8000 count 0x00008000
flush 0x001e0000 count 0x00008000
done memcpy_from_doc_mil
53:fill_inbuf() - nvram:0x00090000 block_count:8
POST: 0xd8, TSC Lo: 43526, Hi: 216
inbuf[0] is 0x9f
flush 0x001e8000 count 0x00008000
flush 0x001f0000 count 0x00008000
flush 0x001f8000 count 0x00008000
done memcpy_from_doc_mil
53:fill_inbuf() - nvram:0x000a0000 block_count:9
POST: 0xd9, TSC Lo: 43526, Hi: 217
inbuf[0] is 0x9c
flush 0x00200000 count 0x00008000
flush 0x00208000 count 0x00008000
flush 0x00210000 count 0x00008000
flush 0x00218000 count 0x00008000
done memcpy_from_doc_mil
53:fill_inbuf() - nvram:0x000b0000 block_count:10
POST: 0xda, TSC Lo: 43526, Hi: 218
inbuf[0] is 0x50
flush 0x00220000 count 0x00008000
flush 0x00228000 count 0x00008000
flush 0x00230000 count 0x00008000
done memcpy_from_doc_mil
53:fill_inbuf() - nvram:0x000c0000 block_count:11
POST: 0xdb, TSC Lo: 43526, Hi: 219
inbuf[0] is 0xbd
flush 0x00238000 count 0x00008000
flush 0x00240000 count 0x00008000
flush 0x00248000 count 0x00008000
flush 0x00250000 count 0x00008000
done memcpy_from_doc_mil
53:fill_inbuf() - nvram:0x000d0000 block_count:12
POST: 0xdc, TSC Lo: 43526, Hi: 220
inbuf[0] is 0xe8
flush 0x00258000 count 0x00008000
flush 0x00260000 count 0x00008000
flush 0x00268000 count 0x00008000
flush 0x00270000 count 0x00008000
flush 0x00278000 count 0x00008000
done memcpy_from_doc_mil
53:fill_inbuf() - nvram:0x000e0000 block_count:13
POST: 0xdd, TSC Lo: 43526, Hi: 221
inbuf[0] is 0x93
flush 0x00280000 count 0x00008000
flush 0x00288000 count 0x00008000
flush 0x00290000 count 0x00008000
flush 0x00298000 count 0x00008000
flush 0x002a0000 count 0x00008000
flush 0x002a8000 count 0x00008000
done memcpy_from_doc_mil
53:fill_inbuf() - nvram:0x000f0000 block_count:14
POST: 0xde, TSC Lo: 43526, Hi: 222
inbuf[0] is 0xdc
flush 0x002b0000 c
flush 0x002b8000 count 0x00008000
flush 0x002c0000 count 0x00008000
flush 0x002c8000 count 0x00008000
flush 0x002d0000 count 0x00008000
flush 0x002d8000 count 0x00008000
done memcpy_from_doc_mil
53:fill_inbuf() - nvram:0x00100000 block_count:15
POST: 0xdf, TSC Lo: 43526, Hi: 223
inbuf[0] is 0xc4
flush 0x002e0000 count 0x00008000
flush 0x002e8000 count 0x00008000
flush 0x002f0000 count 0x00008000
flush 0x002f8000 count 0x00008000
flush 0x00300000 count 0x00008000
done memcpy_from_doc_mil
53:fill_inbuf() - nvram:0x00110000 block_count:16
POST: 0xe0, TSC Lo: 43526, Hi: 224
inbuf[0] is 0x6e
flush 0x00308000 count 0x00008000
flush 0x00310000 count 0x00008000
flush 0x00318000 count 0x000057e0
<1029> fini_bytes
POST: 0xf8, TSC Lo: 43595, Hi: 12
POST: 0xf9, TSC Lo: 4096, Hi: 589824
POST: 0xfa, TSC Lo: 15360, Hi: 589824
command line - [root=/dev/hda2 video=sisfb:800x600-16@60]
Jumping to boot code
POST: 0xfe, TSC Lo: 49446, Hi: 21
