Steve Gehlbach <[EMAIL PROTECTED]> writes:
Ronald G. Minnich wrote: How about using XIP_ROM_SIZE and XIP_ROM_BASE; seems to setup WP caching on variable MTRR 0x203 (mem type=5). Or does this have other effects; maybe use a different option with same code?
XIP is short for Execute in place. And that is exactly what it is designed for.
Fair enough, so we'll use 0x204,5 and separate code. I assume it will speed things up, have to test it in a day or so. As it is, the 5 sec delay makes compression hard to live with.
I am also assuming the Via C3 has the variable MTRRs, that may not be a correct assumption. The Intel book says P6 family.
-Steve
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