Steve Gehlbach <[EMAIL PROTECTED]> writes: > Eric W. Biederman wrote: > > Steve Gehlbach <[EMAIL PROTECTED]> writes: > > > >>Ronald G. Minnich wrote: > >>How about using XIP_ROM_SIZE and XIP_ROM_BASE; seems to setup WP caching on > >>variable MTRR 0x203 (mem type=5). Or does this have other effects; maybe use > a > > >>different option with same code? > > XIP is short for Execute in place. And that is exactly what it is designed > > for. > > > > Fair enough, so we'll use 0x204,5 and separate code. I assume it will speed > things up, have to test it in a day or so. As it is, the 5 sec delay makes > compression hard to live with.
Error. Communications failure. I meant this situation is exactly what it is designed for. > I am also assuming the Via C3 has the variable MTRRs, that may not be a correct > assumption. The Intel book says P6 family. Very good question what does the C3 have? I recall the strange clones not following intels variable mtrrs. Eric _______________________________________________ Linuxbios mailing list [EMAIL PROTECTED] http://www.clustermatic.org/mailman/listinfo/linuxbios
