Ronald G Minnich wrote:
[EMAIL PROTECTED]">On 6 Mar 2001, Eric W. Biederman wrote:
I did some tracing of the alpha at power up and it was getting
read-modify-write cycles when the SROM was zeroing RAM, in an attempt
to do the ECC setup properly. And it wasn't getting ECC errors.
wait! This means that even the BIOS can't do memory init correctly. That's
an exciting thought.
I didn't check but the writes are also useless unless you have ECC
enabled at the time you do them.
makes sense. So my old theory about the kernel covering you were
wrong. This sounds like a needed enhancement to page zero in kernels --
making sure it's write-only.
ron
>From the Intel 440BX and 440GX data sheet:
Note: Any ECC errors received during initialization should be ignored.
Note: When ECC is enabled, the whole DRAM array MUST be first initialized by doing writes before the
DRAM read operations can be performed. This will establish the correlation between 64-bit data
and associated 8-bit ECC code which does not exist after power-on.
Bari
