On 8 Mar 2001, Eric W. Biederman wrote:
> SweepMemory:
> mb
> subq r19, 0x40, r19 /* Decrement pointer */
> whint r18
> mb
> stq r31, 0x00(r18) /* Store same Quadword */
> stq r31, 0x08(r18) /* Store same Quadword */
> [ etc.]
> Does not work reliably to suppress all cache reads.
That's the problem with these tricky hint things. They just don't seem to
ever work reliably on all instances of all versions of a processor. I do
not trust them at all.
> Use Write-Combining with x86 mtrrs to do this.
>
> If you are being clever and not disabling cache you must instrument
> your memory write path and see the code fail sometimes. I assisted
> with a project that attempted to use the alpha memory bus for general
> purpose I/O. It failed because the alpha cannot disable caching on
> RAM.
gag.
Can't we just disable/ignore ECC while we are doing the memory init?
> RAM seems to initialize to 0 on power up so no one notice problems however.
it will init to 0 on power up -- IF you've been off long enough. The
problem comes in the following way: turn off for 5 seconds, turn on.
Enough bits will probably be left to cause trouble. Maybe. I have shown
this to people: turn off machine, turn it back on sometime later, go look
at log_buf in dram (using ICE), notice that there's enough stuff left that
you can kind of read the printk's.
ron
