"Eric W. Biederman" wrote:
>
> Making it conditional sounds like the right move. I'll check it over
> in the coming weeks as I bring up the dual AMD board. Since I have an
> L440GX as well I should be able to test both paths through the code.
>
Thanks.
> Ollie could you give me a hint as to which register needs to get set
> on the Athlons to enable L2 cache. I have made a first pass through
> my docs from AMD (obtained under NDA grumble grumble) and I haven't
> seen anything. At least for the current generation of processors.
>
Does your "docs" have a whole chapter about L2 inti and another about
K7 specific MSR ?? My copy has and they should be enough for L2 init
(I think).
Ollie
