Ollie Lho <[EMAIL PROTECTED]> writes:
> "Eric W. Biederman" wrote:
> >
> > Making it conditional sounds like the right move. I'll check it over
> > in the coming weeks as I bring up the dual AMD board. Since I have an
> > L440GX as well I should be able to test both paths through the code.
> >
>
> Thanks.
>
> > Ollie could you give me a hint as to which register needs to get set
> > on the Athlons to enable L2 cache. I have made a first pass through
> > my docs from AMD (obtained under NDA grumble grumble) and I haven't
> > seen anything. At least for the current generation of processors.
> >
>
> Does your "docs" have a whole chapter about L2 inti and another about
> K7 specific MSR ?? My copy has and they should be enough for L2 init
> (I think).
Basically document number 21656 Athlon Process BIOS Software & debug
developers guide. Has all of that except my chapter 4 on processor
caches, that basically says nothing. I get the impression that for
the slot Athlons you need to do something but for the socket
processors you really don't. There is a changlog entry that says they
removed much of the discussion on L2 init.
So I feel like I should have what I need but it isn't there.
If it wasn't for your earlier comment about not having L2 cache init
I would assume the socket athlons were like the socket athlons and
nothing actually needs to be done.
Eric
