Part of my trouble is that when I enable VGA I don't get a boot log, nothing happens, via serial or vga. Config.lb for MB is below, and config.lb for target follows.
------------------ MB config.lb -------------------------- ## ## Compute the location and size of where this firmware image ## (linuxBIOS plus bootloader) will live in the boot rom chip. ## if USE_FALLBACK_IMAGE default ROM_SECTION_SIZE = FALLBACK_SIZE default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) else default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) default ROM_SECTION_OFFSET = 0 end ## ## Compute the start location and size size of ## The linuxBIOS bootloader. ## default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) ## ## Compute where this copy of linuxBIOS will start in the boot rom ## default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) ## ## Compute a range of ROM that can cached to speed up linuxBIOS, ## execution speed. ## ## XIP_ROM_SIZE must be a power of 2. ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE ## default XIP_ROM_SIZE=65536 default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) ## ## Set all of the defaults for an x86 architecture ## arch i386 end ## ## Build the objects we have code for in this directory. ## driver mainboard.o if HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o ## ## Romcc output ## makerule ./failover.E depends "$(MAINBOARD)/failover.c ./romcc" action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" end makerule ./failover.inc depends "$(MAINBOARD)/failover.c ./romcc" action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" end makerule ./auto.E depends "$(MAINBOARD)/auto.c option_table.h ./romcc" action "./romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" end makerule ./auto.inc depends "$(MAINBOARD)/auto.c option_table.h ./romcc" action "./romcc -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" end ## ## Build our 16 bit and 32 bit linuxBIOS entry code ## mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds ldscript /cpu/x86/32bit/entry32.lds ## ## Build our reset vector (This is where linuxBIOS is entered) ## if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else mainboardinit cpu/x86/32bit/reset32.inc ldscript /cpu/x86/32bit/reset32.lds end ### Should this be in the northbridge code? mainboardinit arch/i386/lib/cpu_reset.inc ## ## Include an id string (For safe flashing) ## mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds ### ### This is the early phase of linuxBIOS startup ### Things are delicate and we test to see if we should ### failover to another image. ### if USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end ### ### O.k. We aren't just an intermediary anymore! ### ## ## Setup RAM ## mainboardinit cpu/x86/fpu/enable_fpu.inc mainboardinit cpu/x86/mmx/enable_mmx.inc mainboardinit ./auto.inc mainboardinit arch/i386/llshell/llshell.inc mainboardinit cpu/x86/mmx/disable_mmx.inc ## ## Include the secondary Configuration files ## dir /pc80 config chip.h chip northbridge/intel/i440bx device pci_domain 0 on device pci 0.0 on end # host bridge device pci 1.0 on end # PCI bridge device pci 10.0 on end # SCSI storage controller device pci 11.0 on end # Ethernet controller device pci 12.0 on end # Audio controller device pci f.0 on # VGA controller chip drivers/pci/onboard device pci f.0 on end register "rom_address" = "0xfff80000" end end device pci 7.0 on # ISA bridge end end chip cpu/intel/socket_PGA370 end end -------------------------------------------------- ----------------- config.lb target --------------- # Config file for asus wkst55 board # This will make a target directory of ./wkst55 target wkst55 mainboard vmware/wkst55 option ROM_SIZE=(512*1024)-(32*1024) romimage "normal" option USE_FALLBACK_IMAGE=0 option ROM_IMAGE_SIZE=0x10000 option LINUXBIOS_EXTRA_VERSION=".0Normal" # payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf # payload ../../../../tg3--ide_disk.zelf # payload ../../../../../lnxieepro100.ebi payload /etc/hosts end romimage "fallback" option USE_FALLBACK_IMAGE=1 option ROM_IMAGE_SIZE=0x10000 option LINUXBIOS_EXTRA_VERSION=".0Fallback" # payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf # payload ../../../../tg3--ide_disk.zelf # payload ../../../../../lnxieepro100.ebia payload /etc/hosts end buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" ----------------------------------------------------------------------- Regards, Ceri ------------------------------ *From:* Lu, Yinghai [mailto:[EMAIL PROTECTED] *Sent:* 28 February 2007 17:27 *To:* Joe Pub; [email protected] *Subject:* RE: [LinuxBIOS] LinuxBIOS and VMWare Boot log and your MB Config.lb? YH ------------------------------ *From:* [EMAIL PROTECTED] [mailto: [EMAIL PROTECTED] *On Behalf Of *Joe Pub *Sent:* Wednesday, February 28, 2007 9:07 AM *To:* [email protected] *Subject:* [LinuxBIOS] LinuxBIOS and VMWare Hi There, Has anyone had any success with VMWare. I have partially implemented the PC87360 SIO chip which has give me serial and I can boot LinuxBIOS up to the elf payload stage. I'm trying to get the VMWare VGA to work at no avail. Has anyone else has success with this. I have added default CONFIG_CONSOLE_VGA=1 default CONFIG_PCI_ROM_RUN=1 to the Optionslb file and adjusted the size of the ROM image by -32KB (sizeof VGA BIOS for VMWare) and also added device pci f.0 on # VGA controller chip drivers/pci/onboard device pci f.0 on end register "rom_address" = "0xfff80000" end end to the Config.lb <http://config.lb/>. When I start VMWare with this image though it does nothing but sit there with no VGA. I have even enabled serial logging back on using CONFIG_CONSOLE_SERIAL8250 but still continue to use CONFIG_PCI_ROM_RUN but nothing then even gets written to the serial port. When does the VGA BIOS rom get called, at what stage? Regards, Joe ______________________________________________________________________ This email has been scanned by the MessageLabs Email Security System. For more information please visit http://www.messagelabs.com/email ______________________________________________________________________
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