Marc Jones schrieb
#define PIRQB 11
to
#define PIRQB 5
This will move audio and eth0 to 5 while USB will be on 10 and 11.
Marc
I changed this and nothing happens - i have put lspci ouput and irq
source in the attachment...
00:0d.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL-8169
Gigabit Ethernet (rev 10)
Subsystem: Realtek Semiconductor Co., Ltd. RTL-8169 Gigabit Ethernet
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop-
ParErr+ Stepping- SERR+ FastB2B-
Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
Latency: 64 (8000ns min, 16000ns max), Cache Line Size: 64 bytes
Interrupt: pin A routed to IRQ 11
Region 0: I/O ports at 1000 [size=256]
Region 1: Memory at fe019000 (32-bit, non-prefetchable) [size=256]
Expansion ROM at ffec0000 [disabled] [size=128K]
Capabilities: [dc] Power Management version 2
Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA
PME(D0-,D1+,D2+,D3hot+,D3cold-)
Status: D0 PME-Enable- DSel=0 DScale=0 PME-
... seems that it doenst change the IRQ?
regards,
steffen
00:01.0 Host bridge: Advanced Micro Devices [AMD] CS5536 [Geode companion] Host
Bridge (rev 30)
Subsystem: Advanced Micro Devices [AMD] CS5536 [Geode companion] Host
Bridge
Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr-
Stepping- SERR- FastB2B-
Status: Cap- 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
Latency: 64
Region 0: I/O ports at ac1c [size=4]
00:01.1 VGA compatible controller: Advanced Micro Devices [AMD] Geode LX Video
(prog-if 00 [VGA])
Subsystem: Advanced Micro Devices [AMD] Geode LX Video
Control: I/O- Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr-
Stepping- SERR- FastB2B-
Status: Cap- 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
Interrupt: pin A routed to IRQ 10
Region 0: Memory at fd000000 (32-bit, non-prefetchable) [size=16M]
Region 1: Memory at fe000000 (32-bit, non-prefetchable) [size=16K]
Region 2: Memory at fe004000 (32-bit, non-prefetchable) [size=16K]
Region 3: Memory at fe008000 (32-bit, non-prefetchable) [size=16K]
Region 4: Memory at fe00c000 (32-bit, non-prefetchable) [size=16K]
00:01.2 Entertainment encryption device: Advanced Micro Devices [AMD] Geode LX
AES Security Block
Subsystem: Advanced Micro Devices [AMD] Geode LX AES Security Block
Control: I/O- Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr-
Stepping- SERR- FastB2B-
Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
Interrupt: pin A routed to IRQ 10
Region 0: Memory at fe010000 (32-bit, non-prefetchable) [size=16K]
00:0d.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL-8169 Gigabit
Ethernet (rev 10)
Subsystem: Realtek Semiconductor Co., Ltd. RTL-8169 Gigabit Ethernet
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr+
Stepping- SERR+ FastB2B-
Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
Latency: 64 (8000ns min, 16000ns max), Cache Line Size: 64 bytes
Interrupt: pin A routed to IRQ 11
Region 0: I/O ports at 1000 [size=256]
Region 1: Memory at fe019000 (32-bit, non-prefetchable) [size=256]
Expansion ROM at ffec0000 [disabled] [size=128K]
Capabilities: [dc] Power Management version 2
Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA
PME(D0-,D1+,D2+,D3hot+,D3cold-)
Status: D0 PME-Enable- DSel=0 DScale=0 PME-
00:0e.0 PCI bridge: Hint Corp HiNT HB4 PCI-PCI Bridge (PCI6150) (rev 04)
(prog-if 00 [Normal decode])
Control: I/O- Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+
Stepping+ SERR+ FastB2B-
Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
Latency: 64
Bus: primary=00, secondary=01, subordinate=01, sec-latency=0
I/O behind bridge: 0000f000-00000fff
Memory behind bridge: fff00000-000fffff
Prefetchable memory behind bridge: 00000000fff00000-00000000000fffff
Secondary status: 66MHz+ FastB2B+ ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- <SERR- <PERR-
BridgeCtl: Parity+ SERR+ NoISA- VGA- MAbort- >Reset- FastB2B-
Capabilities: [dc] Power Management version 1
Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA
PME(D0+,D1+,D2+,D3hot+,D3cold-)
Status: D0 PME-Enable- DSel=0 DScale=0 PME-
Bridge: PM- B3+
Capabilities: [e4] #06 [0094]
Capabilities: [e8] Vital Product Data
00:0f.0 ISA bridge: Advanced Micro Devices [AMD] CS5536 [Geode companion] ISA
(rev 03)
Subsystem: Advanced Micro Devices [AMD] CS5536 [Geode companion] ISA
Control: I/O+ Mem- BusMaster- SpecCycle+ MemWINV- VGASnoop- ParErr+
Stepping- SERR- FastB2B-
Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
Region 0: I/O ports at 1cb0 [size=8]
Region 1: I/O ports at 1400 [size=256]
Region 2: I/O ports at 1c00 [size=64]
Region 3: I/O ports at 1c80 [size=32]
Region 4: I/O ports at 1800 [size=128]
Region 5: I/O ports at 1c40 [size=64]
00:0f.2 IDE interface: Advanced Micro Devices [AMD] CS5536 [Geode companion]
IDE (rev 01) (prog-if 80 [Master])
Subsystem: Advanced Micro Devices [AMD] CS5536 [Geode companion] IDE
Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+
Stepping- SERR- FastB2B-
Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
Latency: 248
Region 0: [virtual] Memory at 000001f0 (32-bit, non-prefetchable)
[disabled] [size=8]
Region 1: [virtual] Memory at 000003f0 (type 3, non-prefetchable)
[disabled] [size=1]
Region 2: [virtual] Memory at 00000170 (32-bit, non-prefetchable)
[disabled] [size=8]
Region 3: [virtual] Memory at 00000370 (type 3, non-prefetchable)
[disabled] [size=1]
Region 4: I/O ports at 1ca0 [size=16]
00:0f.3 Multimedia audio controller: Advanced Micro Devices [AMD] CS5536 [Geode
companion] Audio (rev 01)
Subsystem: Advanced Micro Devices [AMD] CS5536 [Geode companion] Audio
Control: I/O+ Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr+
Stepping- SERR- FastB2B-
Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
Interrupt: pin B routed to IRQ 11
Region 0: I/O ports at 1880 [size=128]
00:0f.4 USB Controller: Advanced Micro Devices [AMD] CS5536 [Geode companion]
OHC (rev 02) (prog-if 10 [OHCI])
Subsystem: Advanced Micro Devices [AMD] CS5536 [Geode companion] OHC
Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr-
Stepping- SERR- FastB2B-
Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
Latency: 0
Interrupt: pin D routed to IRQ 11
Region 0: Memory at fe016000 (32-bit, non-prefetchable) [size=4K]
Capabilities: [40] Power Management version 2
Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA
PME(D0+,D1-,D2-,D3hot+,D3cold+)
Status: D0 PME-Enable- DSel=0 DScale=0 PME-
00:0f.5 USB Controller: Advanced Micro Devices [AMD] CS5536 [Geode companion]
EHC (rev 02) (prog-if 20 [EHCI])
Subsystem: Advanced Micro Devices [AMD] CS5536 [Geode companion] EHC
Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr-
Stepping- SERR- FastB2B-
Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
Latency: 0, Cache Line Size: 32 bytes
Interrupt: pin D routed to IRQ 11
Region 0: Memory at fe017000 (32-bit, non-prefetchable) [size=4K]
Capabilities: [40] Power Management version 2
Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA
PME(D0+,D1-,D2-,D3hot+,D3cold+)
Status: D0 PME-Enable- DSel=0 DScale=0 PME-
/*
* This file is part of the LinuxBIOS project.
*
* Copyright (C) 2007 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <arch/pirq_routing.h>
#include <console/console.h>
#include <arch/io.h>
#include <arch/pirq_routing.h>
#include "../../../southbridge/amd/cs5536/cs5536.h"
/* Platform IRQs */
#define PIRQA 10
#define PIRQB 5
#define PIRQC 10
#define PIRQD 11
/* Map */
#define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */
#define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */
#define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */
#define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */
/* Link */
#define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset INTA# */
#define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset INTB# */
#define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */
#define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */
const struct irq_routing_table intel_irq_routing_table = {
PIRQ_SIGNATURE, /* u32 signature */
PIRQ_VERSION, /* u16 version */
32 + 16 * IRQ_SLOT_COUNT, /* there can be total 6 devices on the
bus */
0x00, /* Where the interrupt router lies (bus) */
(0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */
0x00, /* IRQs devoted exclusively to PCI usage */
0x100B, /* Vendor */
0x002B, /* Device */
0, /* Crap (miniport) */
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */
0x00, /* u8 checksum , this has to set to some
value that would give 0 after the sum of all bytes for this structure
(including checksum) */
{
/* If you change the number of entries, change the IRQ_SLOT_COUNT
above! */
/* bus, dev|fn, {link, bitmap}, {link, bitmap},
{link, bitmap}, {link, bitmap}, slot, rfu */
{0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00,
0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* cpu */
{0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB},
{L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */
{0x00, (0x0D << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {0x00, 0x00}, {0x00,
0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* ethernet */
{0x00, (0x0E << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD},
{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}}, 0x1, 0x0}, /* slot1 */
}
};
unsigned long write_pirq_routing_table(unsigned long addr)
{
int i, j, k, num_entries;
unsigned char pirq[4];
uint16_t chipset_irq_map;
uint32_t pciAddr, pirtable_end;
struct irq_routing_table *pirq_tbl;
pirtable_end = copy_pirq_routing_table(addr);
/* Set up chipset IRQ steering. */
pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C;
chipset_irq_map = (PIRQD << 12 | PIRQC << 8 | PIRQB << 4 | PIRQA);
printk_debug("%s(%08X, %04X)\n", __FUNCTION__, pciAddr,
chipset_irq_map);
outl(pciAddr & ~3, 0xCF8);
outl(chipset_irq_map, 0xCFC);
pirq_tbl = (struct irq_routing_table *)(addr);
num_entries = (pirq_tbl->size - 32) / 16;
/* Set PCI IRQs. */
for (i = 0; i < num_entries; i++) {
printk_debug("PIR Entry %d Dev/Fn: %X Slot: %d\n", i,
pirq_tbl->slots[i].devfn, pirq_tbl->slots[i].slot);
for (j = 0; j < 4; j++) {
printk_debug("INT: %c bitmap: %x ", 'A' + j,
pirq_tbl->slots[i].irq[j].bitmap);
for (k = 0; (!((pirq_tbl->slots[i].irq[j].bitmap >> k)
& 1)) && (pirq_tbl->slots[i].irq[j].bitmap != 0); k++) ; /* Finds lsb in bitmap
to IRQ#. */
pirq[j] = k;
printk_debug("PIRQ: %d\n", k);
}
/* Bus, device, slots IRQs for {A,B,C,D}. */
pci_assign_irqs(pirq_tbl->slots[i].bus,
pirq_tbl->slots[i].devfn >> 3, pirq);
}
/* Put the PIR table in memory and checksum. */
return pirtable_end;
}
--
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