On Saturday 10 November 2007 00:48, Carl-Daniel Hailfinger wrote: > Hi Ward, > > On 08.11.2007 16:51, Carl-Daniel Hailfinger wrote: > > On 08.11.2007 16:22, Ward Vandewege wrote: > >> On Thu, Nov 08, 2007 at 02:05:16PM -0000, LinuxBIOS wrote: > >>> #87: flashrom issues on m57sli-s4 > >>> > >>> I need superiotool output for a board with parallel flash running > >>> under LB. NOW. > >> > >> LinuxBIOS: http://ward.vandewege.net/superiotool-lb.m57sli.dump > >> Proprietary BIOS: > >> http://ward.vandewege.net/superiotool-prop.m57sli.dump > > Can you retest with the following patch applied? Thanks. > > > The "wtf?!?" comment is intentional and designates another bug. However, > > I have no idea which device number we need here. > > Regards, > Carl-Daniel > > > Try to fix a few loose ends on the GA-M57SLI Super I/O GPIO configuration. > > Signed-off-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>
Flash erase on my board was failing reliably. Now it works! Acked-by: Torsten Duwe <[EMAIL PROTECTED]> > --- > > Index: LinuxBIOSv2/src/mainboard/gigabyte/m57sli/Config.lb > =================================================================== > --- LinuxBIOSv2/src/mainboard/gigabyte/m57sli/Config.lb (Revision 2953) > +++ LinuxBIOSv2/src/mainboard/gigabyte/m57sli/Config.lb (Arbeitskopie) > @@ -239,7 +239,9 @@ > device pci 0.0 on end # HT > device pci 1.0 on # LPC > chip superio/ite/it8716f > - device pnp 2e.0 off # > Floppy > + device pnp 2e.0 off # > Floppy and anyLDN > + irq 0x23 = 0x11 > # watchdog from CLKIN, CLKIN = 24 MHz > + #0x24 = 0x1a # > serial flash (SPI only) > io 0x60 = 0x3f0 > irq 0x70 = 6 > drq 0x74 = 2 > @@ -269,6 +271,30 @@ > device pnp 2e.6 on # > Mouse > irq 0x70 = 12 > end > + device pnp 2e.7 on # > GPIO, SPI flash > + irq 0x25 = 0x0 > # pin 84 is not GP10 > + irq 0x26 = 0x43 > # pin 21 is GP26, pin 26 is GP21, pin 27 is GP20 > + irq 0x27 = 0x20 > # pin 13 is GP35 > + #0x28 = 0x0 # > pin 70 is not GP46 > + irq 0x29 = 0x81 > # pin 6,3,128,127,126 is GP63,64,65,66,67 > + #0x2c = 0x1f # > Enable FAN_CTL/FAN_TAC set to 5 (pin 21,23), enable > FAN_CTL/FAN_TAC set to 4 (pin 20,22), pin 48 is PCIRST5#, pin91 is > PCIRSTIN#, VIN7 is internal voltage divider for VCCH5V, pin 95 is ATXPG, > VIN3 is internal voltage divider for VCC5V + > io 0x62 = 0x800 # > simple i/o base > + #io 0x64 = > 0x820 # serial flash io > (SPI only) + #0x71 = > 0x1 # watch dog force timeout (parallel flash > only) + irq > 0x72 = 0x0 # no WDT interrupt > + irq 0xb8 = 0x0 > # GPIO pin set 1 disable internal pullup > + irq 0xbc = 0x01 > # GPIO pin set 5 enable internal pullup > + #0xc0 = 0x0 # > SIO pin set 1 alternate function > + irq 0xc1 = 0x43 > # SIO pin set 2 mixed function > + irq 0xc2 = 0x20 > # SIO pin set 3 mixed function > + #0xc3 = 0x0 # > SIO pin set 4 alternate function > + #0xc8 = 0x0 # > SIO pin set 1 input mode > + irq 0xc9 = 0x0 > # SIO pin set 2 mixed input/output mode > + #0xcb = 0x0 # > SIO pin set 4 input mode > + #0xf0 = 0x10 # > generate SMI# on EC IRQ > + #0xf1 = 0x40 # > SMI# level trigger > + irq 0xf6 = 0x28 > # HWMON alert beep pin location > + end > device pnp 2e.8 off # > MIDI > io 0x60 = 0x300 > irq 0x70 = 10 > @@ -305,6 +331,7 @@ > device i2c 57 on > end end > end # SM > +#wtf?!? we already have device pci 1.1 in the section above > device pci 1.1 on # SM 1 > #PCI device smbus address will depend on addon pci device, do we need to > scan_smbus_bus? # chip > drivers/generic/generic #PCIXA Slot1 -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios
