Re: SiS 630: Problem with enabling the CPU pipeline

[Eric Seppanen]

On Fri, Jan 19, 2001 at 12:53:01PM -0600, Richard A. Smith wrote:
> On Fri, 19 Jan 2001 12:21:24 -0600, Eric Seppanen wrote:
>
> >If you really want to be friendly to bare-bones embedded or thin-client
> >systems, you could even make the fail-safe vs. agressive stuff able to be
> >compiled out, because it's conceivable that an embedded board might not
> >have battery-backed cmos ram-- I don't.
>
> Isn't CMOS normally located in the real-time clock chip?  If so then our
> board dosn't have it either.

On my board (and I'd have to guess that almost all systems are like this)
the RTC and it's associated battery-backed ram (stupidly called "CMOS
ram") are located in the southbridge (Intel PIIX4 in my case).

So I get a functional RTC and ram for free, but I don't have the battery,
so it gets zeroed every power-cycle :)

Eric