"Richard A. Smith" wrote:
> I am hopeing that one of you Gurus can tell me how the hell the A20 line is supposed
>to work
> on the hardware level. We finally got our first prototype board (mostly) populated
>and have
> begun the process of bringing up the design. For reminders its a 400 Mhz Celeron
>using the
> 440bx chipset.
>
> Our first hurdle was that the Southbridge was ignoreing the reset vector. Walking
>all the
> lines showed that all was well the processor was issueing (0xFFFF0). Eventually we
>went
> ahead and looked at the rest of the lines and found that they were all high as well
>except
> for the A20 line which we thought was normal.
>
> We double checked that we had it hooked up just like the Intel ref design.
>
> On a lark we cut the A20Mask line (which is between the southbridge and the cpu)
>this allowd
> the A20 gate line on the processor to go high (it's pulled up) and bingo the
>southbridge
> started responding and fetched the reset vector from our flash.
>
> So questions:
>
> 1) Just what exactly does all the A20 mask stuff do anyway?
>
> 2) Why does the southbridge only respond to addresses in the 0xFFFFxxxx for BIOS
>when the
> data sheets seem to indicate that both ranges should be decoded.
>
> >From page 155 of the 82371AB (southbridge) datasheet:
>
> The 128-Kbyte BIOS memory space is located at (000E0000 - 000FFFFFh) (top of
>1 Mbyte)
> and is aliased at FFFE0000h (top of 4 Gbytes). This 128-Kbyte block is split
>into
> two 64-Kbyte blocks. Accesses to the top 64 Kbytes (000F0000-000FFFFFh) and
>its
> aliased region (FFFF0000- FFFFFFFFh) are always forwarded to the ISA Bus and
>BIOSCS#
> is always generated.
>
> --
> Richard A. Smith Bitworks, Inc.
> [EMAIL PROTECTED] 501.846.5777
> Sr. Design Engineer http://www.bitworks.com
AAAARRRRGGGHHHHH!!!! The infamous Intel BX reference design schematics! We consider
them toxic. Even
Orcad worked to get them debugged. I hope you just used them as a reference and didn't
cut and paste
with them in Orcad. They are great for printing since the schematics by appearance
look perfect,
it's just that the database underneath is all is a mess.
CRESET#, A20M#, A20GATE and PX4_A20M# are all part that pin strap circuit for
processor core and
system bus speed.
If the A20M# input signal is asserted, the processor masks physical address bit 20
(A20#)
before looking up a line in any internal cache and before driving a memory read/write
transaction on the bus. Asserting A20M# emulates the 8086 processors address wraparound
at the one Mbyte boundary. A20M# must only be asserted when the processor is in real
mode. A20M# is not used to mask external snoop addresses.
The IGNNE# and A20M# signals are valid at all times. These signals are normally not
guaranteed recognition at specific boundaries.
The A20M# and IGNNE# signals have different meanings during a reset. A20M# and
IGNNE# are sampled on the active to inactive transition of RESET# to determine the
multiplier for the internal clock frequency, as described in Chapter 5, Configuration
(Pentium
® II Processor Developer's Manual)
Bari Ari
