Armin Schindler <[EMAIL PROTECTED]> writes:
> On Tue, 10 Jul 2001, Ronald G Minnich wrote:
>
> > On Tue, 10 Jul 2001, Armin Schindler wrote:
> >
> > > But I have good news. The 'hlt' error is solved. A stupid init of
> > > the southbridge caused this. I don't know what exactly happened, but
> > > a wrong register value was the error. I rechecked all PCI bridge
> > > init code and now it is working.
> > >
> >
> > can you tell us any more than this? we'd love to know.
> >
> > ron
>
> I cannot tell exactly, I would need to compare every register and
> value used in the init table.
> But what I can tell is, that due to a wrong pointer, some wrong init
> data (wrong register/init value pairs) where used for the southbridge.
>
> According to the STPC specs, the southbridge doesn't use most of these
> registers or they are not documented. So I cannot tell exactly the
> cause.
I can see two possiblilities. Either the timer (not rtc timer) was
disabled and hlt had no interrupts to wake the system up.
Or that hlt is treated specially, because it can be involved in power
management. I believe hlt generates a bus cycle that is turned into a
PCI special cycle, so anything on the PCI bus could have take a
special action when hlt was called.
tripple faulting the cpu is a similiar case. The cpu doesn't actually
reboot but instead it enters a special state that the peripheral chips
have to awaken it up from. And they know it happend because of the
generated pci special cycle. One of the fun things I learned when
figuring out how to reboot my dual-athlon.
Eric
