"Eric S. Raymond" <[EMAIL PROTECTED]> writes:
> Eric Biedermeier suggested I ask here about a BIOS setting on the Tyan
> K7 Thunder motherboard, "Use PCI Interrupt Entries In MP Table".
>
> I'm doing an article about building the ultimate Linux box for Linux
> Journal. This setting turns out to be necessary to eliminate some
> IRQ-sharing conflicts, and I'd like to explain it in the article.
Half of what catches my attention is that I am suprised that you had
an irq sharing conflict with an onboard device.
I choose to have this public is understanding irq routing tends to be very
difficult so having an explanation pop up periodically looks like
a good thing.
In this case the dual athlon motherboard the Tyan Thunder K7/ Tyan
Guiness/ what ever other names it has, has 4 pci interrupt lines that
feed into the AMD766 southbridge. There is a 2 byte routing register in
subfuction 3, offset 0x56, that has a set of mappings from 4 irq pins
to isa interrupts. The stock BIOS mapping is:
PIRQA -> 10
PIRQB -> 5
PIRQC -> 3
PIRQD -> 11
When I looked nothing else uses those ISA interrupts, so having a
conflict would suprise me.
There are two paths for the interrupts through the AMD766.
In the first case the irqs are connected to pins on the ioapic.
So you have:
PIRQA -> ioapic pin 0x10
PIRQB -> ioapic pin 0x11
PIRQC -> ioapic pin 0x12
PIRQD -> ioapic pin 0x13
In the second case the irqs are connected by internal logic to legacy
i82559 interrupt controller, with the exact mapping specified by
subfunction 3 offset 0x56.
The i82559 carry all 16 ISA interrupts have two paths to the local
apic on the cpus.
In the first case used in uniprocessor mode the interrupt flag is
connected to local int 0, which is configured to handle i82559
external interrupts.
In the second case used when both processors become active the i82559
is connected to irqs/pins 0 - 15 of the ioapic. The ioapic the sends
these interrupts of the apic bus to the local apics on each cpu.
All of these connections are active all of the time, the only thing
that change are the mask registers in the interrupt controllers.
As far as I can tell all the "Use PCI Interupt Entries in MP table"
does when enable is:
In the ioapic and probably the i82559 disable interrupts 3,5,10,11.
Assign irqs with higher numbers. (I.e. the pci irq field)
In the ioapic enable pins 0x10 - 0x13 and use the higher numbered
interrupts.
List these interupts in the MP table.
And when "Use PCI Interrupt Entries in MP table" is disabled:
In the ioapic and the i82559 enable interrupts 3,5,10,11.
Assign irqs to the devices with the low numbers.
In the ioapic disable pins 0x10 - 0x13.
Don't list the higher alias in the MP table.
So I don't see how that can be your problem, unless the i82559
acknowledgement logic is locking you up or you moved the problematic
card to a different slot.
Eric
