Question:  What was the resolution to not being able to bring up the serial port?


[EMAIL PROTECTED] writes:

> I'm trying to bring up sdram in 815ep chipset. 
> I have some progress regarding ram initialization, but have many problems
> to resolve. 
> So I hope your comments, advise and help. 
> 
> I made sdram initialization code for 815ep and tested sdram with
> "ram/ramtest.inc". 
> Some part of sdram works. But i can't access whole sdram. here's my output. 
> 
> ---------------------<cut>------------------
> Ram1
> Ram2
> Ram3
> Ram Enable 1
> Ram Enable 2
> Ram Enable 3
> Ram Enable 4
> Ram Enable 5
> Ram4
> Ram5
> Ram6
> Testing SDRAM : 00000000-00003fff
> SDRAM fill:
> 00003fff
> SDRAM verify:
> 00003fff
> Done.         <--- passed without errors. 
> Testing SDRAM : 00100000-0010ffff
> SDRAM fill:
> 0010ffff
> SDRAM verify:
> 00100000
>               <--- system stops while reading from sdram. without any
> error message. 
> ---------------------<cut>------------------
> 
> As you can see above, fill & verify test passed for 0x0 ~ 0x3fff  areas.
> but it fails
> for 0x100000 ~ 0x10ffff areas. in detail, the whole system hangs at
> verification 
> (memory read & check correctness) period of ramtest routine. 
> Do you have any experience similar with this?. 

This feels like one of the tests is staying completely in cache.
Which is possible if you have enabled the mtrrs at this point.  Though
at 64K both of the probably should be cached...

Other thoughts, I have seen things like a top of memory register
that might need to get set.

> Ofcause it's not becuase of faulty sdram. 
>  
> Currently I does not use SPD to get sdram information. I set those 
> information manually. For those values that i set manully for my sdram 
> ( 256M single side at DIMM0 )  is like belows. 
> 
> DRP(0x52)     : 0x0E 
> DRAMT(0x53)   
>       refresh interval : 7.8us  (010 normal operation mode)
>       CAS# latency : 3clk 
> 
> I attached the code. Initially codes are taken from 440bx's raminit.inc. 
> I think it is easy to read for you guys played with other chipset's ram 
> initialization codes. 

Eric

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