[EMAIL PROTECTED] wrote: > I believe it would be possible to build a minimal Alpha > node for a beowulf cluster using a custom programmed ASIC or > FPGA for I/O and Memory management. > > With new ASIC and FPGA technology (up to 300 000 gates) > and opensource intellectual property (www.openip.org) > (free-ip.com)(www.leox.org - For the Leon 32bit processor) > It seems to me that it should be possible to build > a LinuxBIOS board for an alpha processor with space for > oceans of RAM and Multiple ethernet ports. Imagine six > ethernet ports per processor board which would give three > axes of interconnection instead of two. Eight ethernet ports > would give you a Real Hypercube rather than a simple closed > two dimensional surface which is the normal setup known as > a hypercube (cluster). > > I would like to know what you guys think about this idea. > I have not seen any vhdl or other hardware descriptions under > the GPL or LGPL for gigabit ethernet, only 100Mbps ethernet.
The Alpha isn't going to around very much longer. The large FPGAs are very pricey. The ethernet MACs can be done in FPGA but you'd still need a PHY since FPGAs don't offer the analog portion for TX and RX. IMHO it's much simpler, easier and far lower cost to work with commodity chipsets and ethernet controllers for a board design than to spin your own ASIC unless you wish to build for very high volume. A P4 with the 845D chipset with DDR SDRAM and 8 Fast Ethernet controllers sharing the PCI bus is workable. The BOM would be well under $200 plus the cost of DDR and CPU. Bari Ari
