As of today we have linuxbios up on the smartcore-p5. Memtest reports no problems at all on this board. Bharat has been working hard on this board so this is good news. Thanks to Eric Sappenen for contributing his 430tx code.
Caveats. This is a 430TX chipset board. We're finding some problem with the 430tx in that we can't initialize more than one bank of SDRAM. So, for example, we have a 128MB 2-bank DIMM, but if we try to initialize the second bank with the standard NOP, PRECHARGE, CBR sequence the 430tx locks up. This looks like a 430tx bug. If, for example, we do the perfectly legal sequence: set NOP into the control register,'mov 0, %eax', it works fine, but if we do the 'mov 0, %eax' a second time the board locks up. Obviously there is some trick here we don't know, and of course the intel web site is of no use on this score. Obviously, too, the BIOS knows the trick; we don't. So for now, we can only support one-side DIMMs with 64 MB. We plan to fix this, but wanted to get a release out for you all to see. Maybe someone out there will help us fix this! Second problem is that the smartcore-p5 only addresses 256KB of the 512KB FLASH socket. Linux in flash is not possible. We are going to put etherboot in there instead. For our uses, we will use use Etherboot to load our cluster kernel and initrd. We'll let you know more as we get it. I am committing the files now, you can find a sample config file in src/mainboard/digitallogic/smartcore-p5/example.config ron
