"Ian" <[EMAIL PROTECTED]> writes: > >From the porting guide on LANL ... > http://www.acl.lanl.gov/linuxbios/developer/portguides/sbc710/index.html > > "A quick note on the SMBUS" > <pasted in full below> > > ... you mention that RAM is 0x50-0x53 on the SMBus but then go on to > say that sometimes MB's have two SMBus's ... If there is a second bus, > does the RAM still end up at 0x50-0x53 on that bus? (typically) ...?
Hmm. I want to say that is 0x50-0x57... As I recall the specification for memory dimms only has 3 address lines you can change. So yes the spd rom must be addressable in the 0x50-0x57 range, on whatever bus it is on. > > > My other question was on your shift-left .. > "address in the SMBUS packet is shifted left one bit" > > ... that doesn't pick up the carry does it? (my asm is feeling very > rusty). It depends on the instruction. I think it takes a shlc or something like that. Perhaps we have been getting luck. > hmm ... ok ... I'm getting this together. > > > > <pasted in full> > A note on this program. You need to understand a bit about SMBUS to > understand it. If you're doing a port you should understand it anyway! > Here is a quick introduction. > > The data rate is roughly 100 Kbits/second. > SMBUS is a serial bus found on most new motherboards. > SMBUS is also sometimes called I2C, although that usage is being > deprecated. SMBUS is a packet-oriented bus and > is used for communications with many different systems > on PCs, including smart batteries, sensor chips, and SDRAM. As far as I can tell I2C and SMBUS are interrelated standards targeting slightly different audiences. > SMBUS packets contain a 7-bit address for selecting devices. > This address in the > SMBUS packet is shifted left one bit and, for > read operations, OR'ed with > a 1 in the low-order bit. Certain > devices are assigned fixed addresses; SDRAM is one of them. > Currently SDRAM occupies addresses 0x50 to 0x53. > > One thing that complicates SMBUS usage is that a system > may have more than one SMBUS. For example, ASUS motherboards > sometimes have two; IBM thinkpads also seem to have more than one. > The motherboard vendors often obscure > the existence of the SDRAM > SMBUS by hiding it in hardware. On the ASUS CUA we had to find the > enable control for SDRAM SMBUS by using a PCI analyzer to capture > the I/O operations. Right this is one of the more interesting things. Usually a motherboard will have only one i^2c interface and a mux on the i2c line to let you select which bus you really want to talk to. Generally you want to look at the state of the GPIO lines as those seem to control things like that. I have the same issue on the supermicro p4dc6. O.k. Now back to my regularly scheduled sleep. Eric
