On Thu, 14 Mar 2002, Eric Seppanen wrote: > > > > I thought it was setting the MEM and IO bits in the COMMAND register on > > PCI devices, but clearly in general it is not. > > > > Should it? > > It used to. The tree I use turns on the MEM bit if a memory range was > allocated, and the IO bit if an IO range was assigned. I believe I > inherited this code from the old linuxbios PCI code, and in my opinion > it's correct. I don't see any value in not setting the command bits; it > just complicates the possible range of ways that hardware could be > configured when the OS arrives and examines it.
I'm wrong. Sorry. I misinterpreted a problem we're having in Plan 9, but now I see that I do correctly enable most things -- except the Bus Master Enable bit. Some times I do, but on some interfaces I don't so I have to see what's going on. Also, Etherboot gets upset when Bus Master is not set. I have to see if I understand the rules for turning on Bus Master, which I thought I did, but obviously do not. ron
