[EMAIL PROTECTED] writes: > > I'm certain inserting a short delay between operations is the primary > > effect of the inb_p/outb_p functions write to port 0x80. But they > > seem to have some deeper magic significance as well. > > > > Something to do with reliability in older systems. Linus > > commented that if I have a pci post card I shouldn't need to worry > > about it. > > > > Comments like: this functions uses inb_p/outb_p because it must work > > on a lot of hardware. > > > > etc. > > > > So it is clear to me that while a timing delay is part of what > > inb_p/outb_p provide there is some other magic involved. > > No, the magic is that it's an auto-calibrating delay. > > When you have an ISA bus hanging off a PCI bus, the ISA bridge does > what is called "subtractive decode". On cycle 1, the PCI master > presents the address. PCI slaves have cycles 2, 3 and 4 (so-called > fast, medium, and slow devsl options) to assert DEVSEL and "claim" > the trascaction. > > On cycle 5, the ISA bus grabs any cycle in a reasonable range (I/O > port below 64K, memory access below 16M) that someone else hasn't already > grabbed and presents it to the ISA bus. Which takes a while. > > If there s no ISA bridge, on cycle 6 the PCI bus times out and fails the > operation. > > > This is where the magic comes in. If you have an ISA bus, the outb to > port 0x80 will wait an ISA bus cycle. But if you don't, it'll only wait > a PCI bus cycle. > > Either way, it's the speed of the slowest device in the system, so it's > guaranteed to be "enough". But on a PCI-only system, "enough" is a lot > less.
Why is one bus cycle enough? If I plug in a PCI post card when I have ISA bus devices that should break the delay. > That's the magic that Linus was referring to. I understand how the delay works, what I do not understand is why one bus cycle is enough. People seem to use inb_p/outb_p superstiously. Making the assumption that using the will magically make code work. That is what I was refering to. Eric
