>>> + [EMAIL PROTECTED] {
>>> + compatible = "fsl,8572-l2-cache-controller";
>>> + reg = <20000 1000>;
>>> + cache-line-size = <20>; // 32 bytes
>>> + cache-size = <80000>; // L2, 512K
>>> + interrupt-parent = <&mpic>;
>>> + interrupts = <10 2>;
>>> + };
>>
>> Should this node be referenced by an l2-cache property in the cpu
>> node?
>
> No, its a front side cache.
What is a "front side cache"? What exactly does it cache? If it's
a cache for one CPU only, that fact should be shown in the device
tree somehow.
>>> + device_type = "pci";
>>> + #interrupt-cells = <1>;
>>> + #size-cells = <2>;
>>> + #address-cells = <3>;
>>> + reg = <8000 1000>;
>>> + bus-range = <0 ff>;
>>> + ranges = <02000000 0 80000000 80000000 0 20000000
>>> + 01000000 0 00000000 ffc00000 0 00010000>;
>>
>> No prefetchable mem space?
>
> we haven't normally provided prefetch on 85xx/86xx.. will deal with
> this later.
If you don't set up prefetchable memory regions on the PCI from
the firmware, this code is fine, sure. It would be a good plan
to do map all BARs that say they are prefetchable in some
prefetchable PCI window, it gives a nice speed boost, even when
the kernel accesses it as simple non-cacheable space: the PCI
bridges in between can streamline loads from these areas.
In any case, the device tree should be in synch with how the
firmware set up the PCI hardware, and it seems that's what you
have now, so all is fine.
Segher
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