>>>> +static void xive_spapr_update_pending(struct xive_cpu *xc)
>>>> +{
>>>> + u8 nsr, cppr;
>>>> + u16 ack;
>>>> +
>>>> + /* Perform the acknowledge hypervisor to register cycle */
>>>> + ack = be16_to_cpu(__raw_readw(xive_tima + TM_SPC_ACK_OS_REG));
>>>
>>> Why do you need the raw_readw() + be16_to_cpu + mb, rather than one of
>>> the higher level IO helpers?
>>
>> This is one of the many ways to do MMIOs on the TIMA. This memory
>> region defines a set of offsets and sizes for which loads and
>> stores have different effects.
>>
>> See the arch/powerpc/include/asm/xive-regs.h file and
>> arch/powerpc/kvm/book3s_xive_template.c for some more usage.
>
> Sure, much like any IO region. My point is, why do you want this kind
> of complex combo, rather than say an in_be16() or readw_be().
>
The code is inherited from the native backend.
I think this is because we know what we are doing and we skip
the synchronization routines of the higher level IO helpers.
That might not be necessary for sPAPR. Ben ?
Thanks,
C.
