On Thu, Aug 10, 2017 at 09:36:04PM +1000, Benjamin Herrenschmidt wrote: > On Thu, 2017-08-10 at 09:19 +0200, Cédric Le Goater wrote: > > > > > > + /* Perform the acknowledge hypervisor to register cycle */ > > > > > > + ack = be16_to_cpu(__raw_readw(xive_tima + TM_SPC_ACK_OS_REG)); > > > > > > > > > > Why do you need the raw_readw() + be16_to_cpu + mb, rather than one of > > > > > the higher level IO helpers? > > > > > > > > This is one of the many ways to do MMIOs on the TIMA. This memory > > > > region defines a set of offsets and sizes for which loads and > > > > stores have different effects. > > > > > > > > See the arch/powerpc/include/asm/xive-regs.h file and > > > > arch/powerpc/kvm/book3s_xive_template.c for some more usage. > > > > > > Sure, much like any IO region. My point is, why do you want this kind > > > of complex combo, rather than say an in_be16() or readw_be(). > > > > > > > The code is inherited from the native backend. > > > > I think this is because we know what we are doing and we skip > > the synchronization routines of the higher level IO helpers. > > That might not be necessary for sPAPR. Ben ? > > It's a performance optimisation, we know we don't need the > sync,twi,isync crap of the higher level accessor here.
Ok. A comment mentioning this would be good - unless you're very familiar with the code and hardware it's not going to be obvious if the nonstandard IO accessors are for legitimate performance reasons, or just cargo-culting. -- David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_ | _way_ _around_! http://www.ozlabs.org/~dgibson
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