On Wed, 07 Jan 2026 17:59:09 +0100, Christophe Leroy (CS GROUP) wrote: > The QUICC Engine provides interrupts for a few I/O ports. This is > handled via a separate interrupt ID and managed via a triplet of > dedicated registers hosted by the SoC. > > Implement an interrupt driver for it so that those IRQs can then > be linked to the related GPIOs. > > [...]
Applied, thanks! [1/2] soc: fsl: qe: Add an interrupt controller for QUICC Engine Ports [2/2] dt-bindings: soc: fsl: qe: Add an interrupt controller for QUICC Engine Ports Best regards, -- Christophe Leroy (CS GROUP) <[email protected]>
