On 7/20/2026 3:09 PM, Dave Jiang wrote:
>
>
> On 7/17/26 3:26 PM, Terry Bowman wrote:
>> cxl_rch_get_aer_severity() classifies RCH Downstream Port uncorrectable
>> errors as fatal or non-fatal by ANDing uncorrectable status with
>> PCI_ERR_ROOT_FATAL_RCV. This is wrong because PCI_ERR_ROOT_FATAL_RCV is a
>> Root Error Status register bit (bit 6), not a severity bit. ANDing it
>> against uncorrectable status tests a reserved bit and produces incorrect
>> severity classification.
>>
>> Fix by ANDing the unmasked uncor_status against uncor_severity. Per
>> PCIe Base Spec r6.0 Section 7.8.4.4, each bit in the Uncorrectable
>> Error Severity register indicates whether the corresponding error is
>> fatal (1) or non-fatal (0).
>>
>> Fixes: 6ac07883dbb5 ("cxl/pci: Add RCH downstream port error logging")
>> Cc: [email protected]
>> Signed-off-by: Terry Bowman <[email protected]>
>
> Reviewed-by: Dave Jiang <[email protected]>
>
> This can be picked up ahead looks like?
>
Yes.
-Terry
>>
>> ---
>>
>> Changes in v17 -> v18:
>> - New patch.
>> ---
>> drivers/cxl/core/ras_rch.c | 3 ++-
>> 1 file changed, 2 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/cxl/core/ras_rch.c b/drivers/cxl/core/ras_rch.c
>> index 0a8b3b9b63884..44b335d560708 100644
>> --- a/drivers/cxl/core/ras_rch.c
>> +++ b/drivers/cxl/core/ras_rch.c
>> @@ -80,7 +80,8 @@ static bool cxl_rch_get_aer_severity(struct
>> aer_capability_regs *aer_regs,
>> int *severity)
>> {
>> if (aer_regs->uncor_status & ~aer_regs->uncor_mask) {
>> - if (aer_regs->uncor_status & PCI_ERR_ROOT_FATAL_RCV)
>> + if ((aer_regs->uncor_status & ~aer_regs->uncor_mask) &
>> + aer_regs->uncor_severity)
>> *severity = AER_FATAL;
>> else
>> *severity = AER_NONFATAL;
>
