On Fri, 17 Jul 2026 17:27:01 -0500 Terry Bowman <[email protected]> wrote:
> From: Dan Williams <[email protected]> > > The callers of cxl_handle_ras() and cxl_handle_cor_ras() already hold > a struct cxl_port * and struct cxl_dport * for the device being > handled. It seems unlikely that all have both of them given you have handling in the code for dport == NULL. Perhaps reword. > Passing a generic struct device * requires is_cxl_memdev() > to distinguish Endpoints from ports at trace emission time. Threading > port and dport directly enables is_cxl_endpoint(port) and explicit > dport/port branching for cleaner trace dispatch. > > Refactor cxl_handle_ras() and cxl_handle_cor_ras() to accept struct > cxl_port * and struct cxl_dport * directly. The CXL RAS trace event > emission logic is split into three branches: Endpoint events are > identified via is_cxl_endpoint(port) and emit with the memdev, dport > events emit with dport->dport_dev, and Upstream Port events fall back > to port->uport_dev. > > Update cxl_handle_rdport_errors() in ras_rch.c and > cxl_handle_proto_error() in ras.c to pass port and dport to the > refactored functions. Definitely no need to say which files they are in. If we care we can look at the patch. > > RCH Downstream Port correctable trace events now report the dport > device (dport->dport_dev) as a consequence of threading port and dport > through the RAS helpers. The following trace event rework ("cxl: Add > port and dport identifiers to CXL AER trace events") adds explicit > memdev, port, dport, and host fields that provide full context for > all device types. > > Co-developed-by: Terry Bowman <[email protected]> > Signed-off-by: Terry Bowman <[email protected]> > Signed-off-by: Dan Williams <[email protected]> > > --- > > Changes in v17 -> v18: > - New patch. > --- > drivers/cxl/core/core.h | 12 ++++++++---- > drivers/cxl/core/ras.c | 29 +++++++++++++++-------------- > drivers/cxl/core/ras_rch.c | 2 +- > 3 files changed, 24 insertions(+), 19 deletions(-) > > diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h > index 272634ff2615b..5ca1275fd8f35 100644 > --- a/drivers/cxl/core/core.h > +++ b/drivers/cxl/core/core.h > @@ -185,10 +185,12 @@ static inline struct device *dport_to_host(struct > cxl_dport *dport) > #ifdef CONFIG_CXL_RAS > void cxl_ras_init(void); > void cxl_ras_exit(void); > -bool cxl_handle_ras(struct device *dev, void __iomem *ras_base); > +bool cxl_handle_ras(struct cxl_port *port, struct cxl_dport *dport, > + void __iomem *ras_base); > void cxl_do_recovery(struct pci_dev *pdev, struct cxl_port *port, > struct cxl_dport *dport); > -void cxl_handle_cor_ras(struct device *dev, void __iomem *ras_base); > +void cxl_handle_cor_ras(struct cxl_port *port, struct cxl_dport *dport, > + void __iomem *ras_base); > void cxl_dport_map_rch_aer(struct cxl_dport *dport); > void cxl_disable_rch_root_ints(struct cxl_dport *dport); > void cxl_handle_rdport_errors(struct pci_dev *pdev); > @@ -197,13 +199,15 @@ void devm_cxl_dport_ras_setup(struct cxl_dport *dport); > #else > static inline void cxl_ras_init(void) { } > static inline void cxl_ras_exit(void) { } > -static inline bool cxl_handle_ras(struct device *dev, void __iomem *ras_base) > +static inline bool cxl_handle_ras(struct cxl_port *port, struct cxl_dport > *dport, > + void __iomem *ras_base) > { > return false; > } > static inline void cxl_do_recovery(struct pci_dev *pdev, struct cxl_port > *port, > struct cxl_dport *dport) { } > -static inline void cxl_handle_cor_ras(struct device *dev, void __iomem > *ras_base) { } > +static inline void cxl_handle_cor_ras(struct cxl_port *port, struct > cxl_dport *dport, > + void __iomem *ras_base) { } > static inline void cxl_dport_map_rch_aer(struct cxl_dport *dport) { } > static inline void cxl_disable_rch_root_ints(struct cxl_dport *dport) { } > static inline void cxl_handle_rdport_errors(struct pci_dev *pdev) { } > diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c > index 9a142abcf4f8b..6f4a3c1b0bb85 100644 > --- a/drivers/cxl/core/ras.c > +++ b/drivers/cxl/core/ras.c > @@ -232,7 +232,6 @@ void __iomem *to_ras_base(struct cxl_port *port, struct > cxl_dport *dport) > > void cxl_do_recovery(struct pci_dev *pdev, struct cxl_port *port, struct > cxl_dport *dport) > { > - struct device *dev = dport ? dport->dport_dev : port->uport_dev; > void __iomem *ras_base = to_ras_base(port, dport); > > if (!ras_base) { > @@ -241,14 +240,14 @@ void cxl_do_recovery(struct pci_dev *pdev, struct > cxl_port *port, struct cxl_dpo > return; > } > > - if (cxl_handle_ras(dev, ras_base)) > + if (cxl_handle_ras(port, dport, ras_base)) > panic("CXL cachemem error"); > > dev_dbg(&pdev->dev, > "CXL UCE signaled but no CXL RAS status bits set\n"); > } > > -void cxl_handle_cor_ras(struct device *dev, void __iomem *ras_base) > +void cxl_handle_cor_ras(struct cxl_port *port, struct cxl_dport *dport, void > __iomem *ras_base) > { > u32 status; > void __iomem *addr; > @@ -260,10 +259,12 @@ void cxl_handle_cor_ras(struct device *dev, void > __iomem *ras_base) > status = readl(addr); > if (status & CXL_RAS_CORRECTABLE_STATUS_MASK) { > writel(status & CXL_RAS_CORRECTABLE_STATUS_MASK, addr); > - if (is_cxl_memdev(dev)) > - trace_cxl_aer_correctable_error(to_cxl_memdev(dev), > status); > + if (is_cxl_endpoint(port)) > + > trace_cxl_aer_correctable_error(to_cxl_memdev(port->uport_dev), status); > + else if (dport) > + trace_cxl_port_aer_correctable_error(dport->dport_dev, > status); > else > - trace_cxl_port_aer_correctable_error(dev, status); > + trace_cxl_port_aer_correctable_error(port->uport_dev, > status); > } > } > > @@ -288,7 +289,7 @@ static void header_log_copy(void __iomem *ras_base, u32 > *log) > * Log the state of the RAS status registers and prepare them to log the > * next error status. Return 1 if reset needed. > */ > -bool cxl_handle_ras(struct device *dev, void __iomem *ras_base) > +bool cxl_handle_ras(struct cxl_port *port, struct cxl_dport *dport, void > __iomem *ras_base) > { > u32 hl[CXL_HEADERLOG_TRACE_SIZE_U32] = {}; > void __iomem *addr; > @@ -315,10 +316,12 @@ bool cxl_handle_ras(struct device *dev, void __iomem > *ras_base) > } > > header_log_copy(ras_base, hl); > - if (is_cxl_memdev(dev)) > - trace_cxl_aer_uncorrectable_error(to_cxl_memdev(dev), status, > fe, hl); > + if (is_cxl_endpoint(port)) > + > trace_cxl_aer_uncorrectable_error(to_cxl_memdev(port->uport_dev), status, fe, > hl); > + else if (dport) > + trace_cxl_port_aer_uncorrectable_error(dport->dport_dev, > status, fe, hl); > else > - trace_cxl_port_aer_uncorrectable_error(dev, status, fe, hl); > + trace_cxl_port_aer_uncorrectable_error(port->uport_dev, status, > fe, hl); > > writel(status & CXL_RAS_UNCORRECTABLE_STATUS_MASK, addr); > > @@ -351,7 +354,7 @@ pci_ers_result_t cxl_error_detected(struct pci_dev *pdev, > * chance the situation is recoverable dump the status of the > RAS > * capability registers and bounce the active state of the > memdev. > */ > - ue = cxl_handle_ras(port->uport_dev, to_ras_base(port, NULL)); > + ue = cxl_handle_ras(port, NULL, to_ras_base(port, NULL)); > } > > /* > @@ -382,10 +385,8 @@ EXPORT_SYMBOL_NS_GPL(cxl_error_detected, "CXL"); > static void cxl_handle_proto_error(struct pci_dev *pdev, struct cxl_port > *port, > struct cxl_dport *dport, int severity) > { > - struct device *dev = dport ? dport->dport_dev : port->uport_dev; > - > if (severity == AER_CORRECTABLE) > - cxl_handle_cor_ras(dev, to_ras_base(port, dport)); > + cxl_handle_cor_ras(port, dport, to_ras_base(port, dport)); > else > cxl_do_recovery(pdev, port, dport); > } > diff --git a/drivers/cxl/core/ras_rch.c b/drivers/cxl/core/ras_rch.c > index f2d2fb83758b9..f4b98f2c11a1c 100644 > --- a/drivers/cxl/core/ras_rch.c > +++ b/drivers/cxl/core/ras_rch.c > @@ -118,7 +118,7 @@ void cxl_handle_rdport_errors(struct pci_dev *pdev) > > pci_print_aer(pdev, severity, &aer_regs); > if (severity == AER_CORRECTABLE) > - cxl_handle_cor_ras(&pdev->dev, to_ras_base(port, dport)); > + cxl_handle_cor_ras(dport->port, dport, to_ras_base(port, > dport)); > else > cxl_do_recovery(pdev, dport->port, dport); > }
