The cache event table maps L1-icache-prefetches to 0x634, PMC6 select
52. The manual (MPC7450UM Rev. 5, Table 11-14) calls that event
"Prefetch engine request" and says it "counts new prefetches allocated
in the prefetch unit". It is the first of six events about the L2
prefetch engine (selects 52-57), and the MPC7450 has no instruction
cache prefetch event.
On a 7448, a pointer chase over 64-byte nodes counts r634 at 0.00 per
load when the working set fits in the 1 MB L2, and at 1.00 per load,
one per L2 demand miss, at 4 MB.
The engine starts a prefetch only when an access misses in every cache,
fetches from the bus, and also fills the L3 if there is one (section
3.6.3.2), so it is a last-level prefetch with or without an L3. Report
it as LL-prefetches, and L1-icache-prefetches as not supported.
Fixes: 7325927e5a20 ("perf_counter: powerpc: Add processor back-end for MPC7450
family")
Signed-off-by: Matt Turner <[email protected]>
---
arch/powerpc/perf/mpc7450-pmu.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/perf/mpc7450-pmu.c b/arch/powerpc/perf/mpc7450-pmu.c
index 564f6dac3a00..5a882d934645 100644
--- a/arch/powerpc/perf/mpc7450-pmu.c
+++ b/arch/powerpc/perf/mpc7450-pmu.c
@@ -370,12 +370,12 @@ static u64
mpc7450_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
[C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */
[C(OP_READ)] = { 0x129, 0x115 },
[C(OP_WRITE)] = { -1, -1 },
- [C(OP_PREFETCH)] = { 0x634, 0 },
+ [C(OP_PREFETCH)] = { 0, 0 },
},
[C(LL)] = { /* RESULT_ACCESS RESULT_MISS */
[C(OP_READ)] = { 0, 0 },
[C(OP_WRITE)] = { 0, 0 },
- [C(OP_PREFETCH)] = { 0, 0 },
+ [C(OP_PREFETCH)] = { 0x634, 0 },
},
[C(DTLB)] = { /* RESULT_ACCESS RESULT_MISS */
[C(OP_READ)] = { 0, 0x312 },
--
2.55.0
