PMC6 repeats five L3 events at a second select value that the alternatives table doesn't list:
0x61f L3 hits, also 0x503 and 0x603 0x620 L3 misses, also 0x514 and 0x61e 0x621 L3 instruction misses, also 0x505 and 0x605 0x622 L3 data misses, also 0x507 and 0x607 0x625 L3 touch hits, also 0x50e and 0x60e Each is the same event as the PMC5 code, so add them to its row. The scheduler can then move them to PMC5 when PMC6 is taken. Not tested on hardware with an L3; the 7448 has none. Signed-off-by: Matt Turner <[email protected]> --- arch/powerpc/perf/mpc7450-pmu.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/powerpc/perf/mpc7450-pmu.c b/arch/powerpc/perf/mpc7450-pmu.c index 27337a03ebde..b2fe977cea16 100644 --- a/arch/powerpc/perf/mpc7450-pmu.c +++ b/arch/powerpc/perf/mpc7450-pmu.c @@ -185,18 +185,18 @@ static int mpc7450_get_constraint(u64 event, unsigned long *maskp, static const unsigned int event_alternatives[][MAX_ALT] = { { 0x217, 0x317 }, /* PM_L1_DCACHE_MISS */ { 0x502, 0x602 }, /* PM_L2_HIT */ - { 0x503, 0x603 }, /* PM_L3_HIT */ + { 0x503, 0x603, 0x61f }, /* PM_L3_HIT */ { 0x504, 0x604 }, /* PM_L2_ICACHE_MISS */ - { 0x505, 0x605 }, /* PM_L3_ICACHE_MISS */ + { 0x505, 0x605, 0x621 }, /* PM_L3_ICACHE_MISS */ { 0x506, 0x606 }, /* PM_L2_DCACHE_MISS */ - { 0x507, 0x607 }, /* PM_L3_DCACHE_MISS */ + { 0x507, 0x607, 0x622 }, /* PM_L3_DCACHE_MISS */ { 0x50a, 0x623 }, /* PM_LD_HIT_L3 */ { 0x50b, 0x624 }, /* PM_ST_HIT_L3 */ { 0x50d, 0x60d }, /* PM_L2_TOUCH_HIT */ - { 0x50e, 0x60e }, /* PM_L3_TOUCH_HIT */ + { 0x50e, 0x60e, 0x625 }, /* PM_L3_TOUCH_HIT */ { 0x512, 0x612 }, /* PM_INT_LOCAL */ { 0x513, 0x61d }, /* PM_L2_MISS */ - { 0x514, 0x61e }, /* PM_L3_MISS */ + { 0x514, 0x61e, 0x620 }, /* PM_L3_MISS */ }; /* -- 2.55.0
