ARIA is a MPC5121 based COM Express module by Dave/DENX.
Signed-off-by: Andrea Scian <andrea.sc...@dave.eu>
Signed-off-by: Wolfgang Denk <w...@denx.de>
Cc: Grant Likely <grant.lik...@secretlab.ca>
Cc: John Rigby <jcri...@gmail.com>
---
arch/powerpc/boot/dts/aria.dts | 410 ++++++++++++++++++++++++++++++++++++++++
1 files changed, 410 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/boot/dts/aria.dts
diff --git a/arch/powerpc/boot/dts/aria.dts b/arch/powerpc/boot/dts/aria.dts
new file mode 100644
index 0000000..6c6b5e4
--- /dev/null
+++ b/arch/powerpc/boot/dts/aria.dts
@@ -0,0 +1,407 @@
+/*
+ * Aria Device Tree Source
+ *
+ * Copyright 2009 Dave Srl www.dave.eu
+ * Copyright 2009 Wolfgang Denk <w...@denx.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+/dts-v1/;
+
+/ {
+ model = "aria";
+ compatible = "davedenx,aria";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ aliases {
+ ethernet0 = &enet;
+
+ serial0 = &serial0;
+ serial1 = &serial1;
+
+ pci = &pci;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ PowerPC,5...@0 {
+ device_type = "cpu";
+ reg = <0>;
+ d-cache-line-size = <0x20>; // 32 bytes
+ i-cache-line-size = <0x20>; // 32 bytes
+ d-cache-size = <0x8000>; // L1, 32K
+ i-cache-size = <0x8000>; // L1, 32K
+ timebase-frequency = <49500000>;// 49.5 MHz (csb/4)
+ //bus-frequency = <198000000>; // 198 MHz csb bus
+ //clock-frequency = <396000000>; // 396 MHz ppc
core
+ bus-frequency = <158000000>;
+ clock-frequency = <316000000>;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x00000000 0x10000000>; // 256MB at 0
+ };
+
+ m...@20000000 {
+ device_type = "mbx";
+ compatible = "fsl,mpc5121-mbx";
+ reg = <0x20000000 0x4000>;
+ interrupts = <66 0x8>;
+ interrupt-parent = < &ipic >;
+ };
+
+ s...@30000000 {
+ compatible = "fsl,mpc5121-sram";
+ reg = <0x30000000 0x20000>; // 128K at 0x30000000
+ };
+
+ n...@40000000 {
+ //compatible = "fsl,mpc5121rev2-nfc";
+ compatible = "fsl,mpc5121-nfc";
+ reg = <0x40000000 0x100000>; // 1M at 0x40000000
+ interrupts = <6 8>;
+ interrupt-parent = < &ipic >;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ write-size = <2048>;
+ spare-size = <64>;
+ chips = <1>;
+ n...@0 {
+ label = "nand";
+ reg = <0x00000000 0x08000000>; // 128 MB
+ };
+ };
+
+ local...@80000020 {
+ compatible = "fsl,mpc5121-localbus";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ reg = <0x80000020 0x40>;
+
+ ranges = <0x0 0x0 0xF8000000 0x08000000>;
+
+ fl...@0,0 {
+ compatible = "cfi-flash";
+ reg = <0 0x0 0x8000000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ bank-width = <2>;
+ device-width = <2>;
+ partit...@0 {
+ label = "user";
+ reg = <0x00000000 0x07000000>; // 112 MiB for
user data
+ };
+ partit...@07000000 {
+ label = "rootfs";
+ reg = <0x07000000 0x00c00000>; // 12 MiB for
root file system
+ };
+ partit...@07c00000 {
+ label = "kernel";
+ reg = <0x07c00000 0x00300000>; // 3 MiB for
kernel
+ };
+ partit...@07f00000 {
+ label = "u-boot";
+ reg = <0x07f00000 0x000c0000>; // 768 KiB for
u-boot w/ env
+ read-only;
+ };
+ partit...@07fc0000 {
+ label = "device-tree";
+ reg = <0x07fc0000 0x00040000>; // 256 KiB for
device tree
+ };
+ };
+ };
+
+ s...@80000000 {
+ compatible = "fsl,mpc5121-immr";
+ device_type = "soc";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ #interrupt-cells = <2>;
+ ranges = <0x0 0x80000000 0x400000>;
+ reg = <0x80000000 0x400000>;
+ bus-frequency = <66000000>; // 66 MHz ips bus
+
+
+ // IPIC
+ // interrupts cell = <intr #, sense>
+ // sense values match linux IORESOURCE_IRQ_* defines:
+ // sense == 8: Level, low assertion
+ // sense == 2: Edge, high-to-low change
+ //
+ ipic: interrupt-control...@c00 {
+ compatible = "fsl,mpc5121-ipic", "fsl,ipic";
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ reg = <0xc00 0x100>;
+ };
+
+ r...@a00 { // Real time clock
+ compatible = "fsl,mpc5121-rtc";
+ reg = <0xa00 0x100>;
+ interrupts = <79 0x8 80 0x8>;
+ interrupt-parent = < &ipic >;
+ };
+
+ re...@e00 { // Reset module
+ compatible = "fsl,mpc5121-reset";
+ reg = <0xe00 0x100>;
+ };
+
+ cl...@f00 { // Clock control
+ compatible = "fsl,mpc5121rev2-clock",
"fsl,mpc5121-clock";
+ reg = <0xf00 0x100>;
+ };
+
+ p...@1000{ //Power Management Controller
+ compatible = "fsl,mpc5121-pmc";
+ reg = <0x1000 0x100>;
+ interrupts = <83 0x2>;
+ interrupt-parent = < &ipic >;
+ };
+
+ g...@1100 {
+ compatible = "fsl,mpc5121-gpio";
+ reg = <0x1100 0x100>;
+ interrupts = <78 0x8>;
+ interrupt-parent = < &ipic >;
+ };
+
+ ms...@1300 {
+ compatible = "fsl,mpc5121-mscan";
+ cell-index = <0>;
+ interrupts = <12 0x8>;
+ interrupt-parent = < &ipic >;
+ reg = <0x1300 0x80>;
+ };
+
+ ms...@1380 {
+ compatible = "fsl,mpc5121-mscan";
+ cell-index = <1>;
+ interrupts = <13 0x8>;
+ interrupt-parent = < &ipic >;
+ reg = <0x1380 0x80>;
+ };
+
+ // this is here for reference only
+// s...@1500 {
+// compatible = "fsl,mpc5121-sdhc";
+// interrupts = <8 0x8>;
+// interrupt-parent = < &ipic >;
+// reg = <0x1500 0x100>;
+// };
+
+ i...@1700 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,mpc5121-i2c", "fsl-i2c";
+ cell-index = <0>;
+ reg = <0x1700 0x20>;
+ interrupts = <9 0x8>;
+ interrupt-parent = < &ipic >;
+ fsl5200-clocking;
+
+ r...@68 {
+ compatible = "stm,m41t80";
+ reg = <0x68>;
+ };
+ };
+
+ i...@1720 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,mpc5121-i2c", "fsl-i2c";
+ cell-index = <1>;
+ reg = <0x1720 0x20>;
+ interrupts = <10 0x8>;
+ interrupt-parent = < &ipic >;
+ fsl5200-clocking;
+ };
+
+ i...@1740 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,mpc5121-i2c", "fsl-i2c";
+ cell-index = <2>;
+ reg = <0x1740 0x20>;
+ interrupts = <11 0x8>;
+ interrupt-parent = < &ipic >;
+ fsl5200-clocking;
+ };
+
+ i2ccont...@1760 {
+ compatible = "fsl,mpc5121-i2c-ctrl";
+ reg = <0x1760 0x8>;
+ };
+
+ a...@2000 {
+ compatible = "fsl,mpc5121-axe";
+ reg = <0x2000 0x100>;
+ interrupts = <42 0x8>;
+ interrupt-parent = < &ipic >;
+ };
+
+ d...@2100 {
+ device_type = "display";
+ compatible = "fsl-diu";
+ reg = <0x2100 0x100>;
+ interrupts = <64 0x8>;
+ interrupt-parent = < &ipic >;
+ };
+
+ m...@2800 {
+ device_type = "mdio";
+ compatible = "fsl,mpc5121-fec-mdio";
+ reg = <0x2800 0x800>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ phy: ethernet-...@0 {
+ reg = <23>;
+ device_type = "ethernet-phy";
+ };
+ };
+
+ enet: ether...@2800 {
+ device_type = "network";
+ compatible = "fsl,mpc5121-fec";
+ reg = <0x2800 0x800>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <4 0x8>;
+ interrupt-parent = < &ipic >;
+ phy-handle = < &phy >;
+ fsl,align-tx-packets = <4>;
+ };
+
+ // 5121e has two dr usb modules
+ // We use only USB0
+
+ // USB1 using external ULPI PHY
+ //u...@3000 {
+ // device_type = "usb";
+ // compatible = "fsl-usb2-dr";
+ // reg = <0x3000 0x1000>;
+ // #address-cells = <1>;
+ // #size-cells = <0>;
+ // interrupt-parent = < &ipic >;
+ // interrupts = <43 0x8>;
+ // dr_mode = "otg";
+ // phy_type = "ulpi";
+ //};
+
+ // USB0 using internal UTMI PHY
+ u...@4000 {
+ device_type = "usb";
+ compatible = "fsl-usb2-dr";
+ reg = <0x4000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupt-parent = < &ipic >;
+ interrupts = <44 0x8>;
+ dr_mode = "host";
+ phy_type = "utmi_wide";
+ //port0;
+ };
+
+ // IO control
+ io...@a000 {
+ compatible = "fsl,mpc5121-ioctl";
+ reg = <0xA000 0x1000>;
+ };
+
+ p...@10200 {
+ compatible = "fsl,mpc5121-pata";
+ reg = <0x10200 0x100>;
+ interrupts = <5 0x8>;
+ interrupt-parent = < &ipic >;
+ };
+
+ // 512x PSCs are not 52xx PSCs compatible
+ // PSC3 serial port A aka ttyPSC0
+ serial0: ser...@11300 {
+ device_type = "serial";
+ compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
+ // Logical port assignment needed until driver
+ // learns to use aliases
+ port-number = <0>;
+ cell-index = <3>;
+ reg = <0x11300 0x100>;
+ interrupts = <40 0x8 71 0x8>;
+ interrupt-parent = < &ipic >;
+ rx-fifo-size = <16>;
+ tx-fifo-size = <16>;
+ nodcd;
+ };
+
+ // PSC4 serial port B aka ttyPSC1
+ serial1: ser...@11400 {
+ device_type = "serial";
+ compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
+ // Logical port assignment needed until driver
+ // learns to use aliases
+ port-number = <1>;
+ cell-index = <4>;
+ reg = <0x11400 0x100>;
+ interrupts = <40 0x8 32 0x8>;
+ interrupt-parent = < &ipic >;
+ rx-fifo-size = <16>;
+ tx-fifo-size = <16>;
+ nodcd;
+ };
+
+ // PSC5 in ac97 mode
+ a...@11500 {
+ device_type = "sound";
+ compatible = "fsl,mpc5121-psc-ac97", "fsl,mpc5121-psc";
+ cell-index = <5>;
+ reg = <0x11500 0x100>;
+ interrupts = <40 0x8>;
+ interrupt-parent = < &ipic >;
+ fsl,mode = "ac97-slave";
+ rx-fifo-size = <384>;
+ tx-fifo-size = <384>;
+ };
+
+ pscf...@11f00 {
+ compatible = "fsl,mpc5121-psc-fifo";
+ reg = <0x11f00 0x100>;
+ interrupts = <40 0x8>;
+ interrupt-parent = < &ipic >;
+ };
+
+ d...@14000 {
+ compatible = "mpc512x-dma";
+ reg = <0x14000 0x1800>;
+ interrupts = <65 0x8>;
+ interrupt-parent = < &ipic >;
+ };
+
+ };
+
+ pci: p...@80008500 {
+ interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
+ interrupt-map = <
+ >;
+ interrupt-parent = < &ipic >;
+ interrupts = <1 0x8>;
+ bus-range = <0 0>;
+ ranges = <0x42000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
+ 0x02000000 0x0 0xb0000000 0xb0000000 0x0 0x10000000
+ 0x01000000 0x0 0x00000000 0x84000000 0x0 0x01000000>;
+ clock-frequency = <66666666>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <0x80008500 0x100>;
+ compatible = "fsl,mpc5121-pci";
+ device_type = "pci";
+ };
+};
--
1.6.0.6
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