>>>>> "GL" == Grant Likely <[EMAIL PROTECTED]> writes:
Hi, GL> So what direction do we (as the community) want to go for GL> supporting Xilinx IP in the Linux kernel? GL> IIRC, Xilinx intends to get drivers submitted into mainline. GL> (Based on their cross-platform driver support code). It is GL> unknown which and how many drivers for different IP versions will GL> be submitted. Yes, that's also what I hear from the Xilinx guys - But action speaks louder than words. It's not like the V2P is new technology anymore. GL> However, the xilinx driver code is verbose and does not match well GL> with the rest of the Linux code base. Yeah, the Xilinx stuff/flow definately doesn't fit the kernel. GL> If we reject the Xilinx driver code, then we either have to do GL> without Xilinx support in mainline, or we need to write new GL> drivers that address the above issues (support multiple IP GL> versions, etc). The Xilinx support in mainline right now does not GL> use any Xilinx code. (Xilinx PIC and UART). I think the best option is to simply forget about the Xilinx code, see the FPGAs as any other PPC system and write normal device drivers for it. Your platform bus stuff and my (to-be-mainlined) uartlite driver is a first step in this direction.. -- Bye, Peter Korsgaard _______________________________________________ Linuxppc-embedded mailing list Linuxppc-embedded@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-embedded
