A little further on IRQ mapping. I was incorrect in saying enet_tx is at
19. According to MPC8555ERM.pdf the TSEC1_tx, TSEC_rx and DUART are at
13 TSEC1_tx (maps to 93)
14 TSEC1_rx (maps to 94)
26 DUART (maps to 106)
A 'cat /proc/interrupts' shows this 93, 94 & 106 mapping:
[EMAIL PROTECTED]:~# cat /proc/interrupts
CPU0
2: 0 i8259 Edge 82c59 secondary cascade
32: 0 CPM2 SIU Level ichar
93: 10701 OpenPIC Level enet_tx
94: 13945 OpenPIC Level enet_rx
98: 0 OpenPIC Level enet_error
106: 542 OpenPIC Level serial
107: 0 OpenPIC Level i2c-mpc
110: 0 OpenPIC Level cpm2_cascade
128: 0 OpenPIC Level <NULL>
BAD: 0
[EMAIL PROTECTED]:~#
Looking at arch/ppc/platforms/85xx/mpc85xx_cds_common.c, I can see the
mpc85xx_cds_openpic[] array and since CONFIG_PCI is defined, the first
four entries for IRQ0..3 (or INTA, INTB, INTC & INTD) have non-zero
entries containing (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), which
should be OK.
Down a little further in this file is mpc85xx_cds_init_IRQ and it we do
not have CONFIG_MPC8548 defined, so we should be calling
openpic_set_sources(0, 32, OpenPIC_ADDR + 0x10200)
followed by calling
openpic_set_sources(48, 12, OpenPIC_ADDR + 0x10000)
This leads to a couple of new questions.
1. We have no 8259 in our design. Is this a concern as we are always
calling the i8259_init() routine.
2. The 'cat /proc/interrupts' shows 82c59 secondary cascade. Again, does
this matter?
3. The offset between TSEC1_tx of 13-->93 is a constant of 80 decimal.
Is this a clue to what the irq should be set to for external IRQ0 in
this design?
Charles Krinke
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