Joakim Tjernlund wrote:
> OK, here it goes.
No, this isn't correct......
> + /* The 20 msb of MD_EPN and DAR must be the same when rfi is
> + * executed. The dcxx instructions don't set DAR when they
> + * cause a DTLB Miss so copy them from MD_EPN.
No, don't be screwing around with these registers.
> -#ifdef CONFIG_8xx
> +#ifdef CONFIG_8xx_CPU6
What is this all about? The CPU6 errata is a clearly defined
problem on well known silicon revisions. Don't be using it where
it isn't intended.
Please try again..........thanks.
-- Dan
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