After reading this I guess I need to further clarify what happens.....
Dan Malek wrote:
> ... The reason it "works" for you is you found the
> most likely case where you took a DTLB miss, followed by a DTLB Error
> to the same page...
What happens in these cases (which occurs like almost all of the time),
is there is "leftover" information in the control/status registers from
previous exceptions that causes the fault processing to take place
properly. In some error conditions, the leftover information isn't
exactly correct, causing the page fault handler to look up wrong
information or the dcbz/dcbt to do their thing on the wrong address.
If you are not running a specific test case and precisely testing
for the results of the operation, you may not notice this or at some
time in the future notice erratic system behavior that is impossible
to explain. The "normal" instructions have exactly one well documented
failure case, in the case of DTLBError, the MD_EPN sometimes doesn't
get the proper status, but we know the DAR does, so we can copy the
bits we need from the DAR to the EPN to properly process the fault.
The cache instructions have never been normal instructions. In some
versions of silicon they won't generate a fault, some will allow cache
operations to uncached spaces, some will fault but not provide the
proper status in any MMU register. Sometimes they work, it all depends
upon the state of the cache line and TLB. The cases most likely to
fail are the ones that are the hardest to create.
I've spent way too much time working on this on many versions of
silicon with the assistance of people from Motorola. It isn't a trivial
problem to detect, quantify and document so someone else can repeat
the exercise. Through the first four major versions of 860 silicon
(and countless minor versions) the wrong behavior I discussed was
fixed in the next release, only to have something else unexpected appear.
Since I didn't want a career in cache instruction debugging (and I had
products to get to market), the solution was to simply not use these
instructions.
Thanks.
-- Dan
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