I think we need to hold off on this particular patch for a few days. I took a look at the manual section you're referencing here, and sure enough, it says that you shouldn't set both bits in the same mtspr instruction. The manual says this in more than one place, in fact. However, that seemed a little bit odd to me, so I talked with a few of the hardware designers for the 745x family. They assure me that the manual statement is false. The normal code that sets ICE/ICFI/ DCE/DCFI all on one mtspr should be fully functional on this processor family. I'm still working on confirming this and getting some history on *why* the manual says that, but for now I'd say it's a pretty good bet that the manual is in error. I will let you know if I find out this is not the case.
You are correct, though, in that an isync is needed prior to the write of HID0[ICE]. It's probably missing because it's not listed in the synchronization table in chapter 2 of the manual. For what it's worth, as soon as I can confirm this, I will make sure the publications team here at Freescale is made aware of the error so it can be corrected in the next printing of the manual. I will also have the synchronization table updated as it also has incorrect information. Thanks, B
