There are some silicon issues on the PPC405 in V4 with PVR 0x20011430 which are documented in Xilinx solution record 20658. All these issues are fixed in silicon where the PPC405 has a PVR of 0x20011470.
Said that it's not true that the caches cannot be used in silicon with PVR 0x20011430. The problem is a corner case which does not show in typical designs. - Peter Aidan Williams wrote: >Anantharaman Chetan-W16155 wrote: > > >>Has anyone successfully ported a Linux 2.4 Kernel on a Xilinx Virtex-4 >>FX series FPGA?s, PPC405 processor? >> >> >> > >Yes, see >http://ozlabs.org/pipermail/linuxppc-embedded/2006-April/022583.html > >Note that there are silicon bugs that prevent caches being used in some >chips. > > > >>More specifically, the FX100 FPGA? >> >> > >I don't have one of those, sorry. > >- aidan > >_______________________________________________ >Linuxppc-embedded mailing list >Linuxppc-embedded at ozlabs.org >https://ozlabs.org/mailman/listinfo/linuxppc-embedded > > > >
