On Wed, Apr 01, 2015 at 10:18:27PM +0000, Daniel Le wrote:
> My PTP slave clock appears to lose sync with a grandmaster clock
> when under heavy load and worse it can't recover. The sync is good
> when there is low or no other traffic. This slave clock uses
> software timestamping to adjust the host system time. The PTP
> transmit and receive packets are time stamped by a non-1588 aware
> NIC's FPGA clock which is sync'd to the host system clock, i.e. the
> NIC regularly gets host system time to step/slew to it.
This sounds fishy to me. You say your slave uses SW time stamping,
but that the FPGA provides time stamps. That is HW time stamping!
Also, since the Linux system time is purely software, how do you get
its time into the FPGA? By using phc2sys?
> The log shows:
> - port <port#>: SLAVE to UNCALIBRATED on SYNCHRONIZATION_FAULT
>
> and the following repetitive messages:
> - clockcheck: clock jumped forward or running faster than expected!
> - clockcheck: clock jumped backward or running slower than expected!
>
> I would appreciate information to debug this, as well an explanation of what
> may be happening.
That message comes from the function, clockcheck_sample(), in
clockcheck.c. It does the following:
/* Check the sanity of the synchronized clock by comparing its
uncorrected frequency with the system monotonic clock. If
the synchronized clock is the system clock, the measured
frequency offset will be the current frequency correction of
the system clock. */
This is sanity check against CLOCK_MONOTONIC. Probably there is a bug
in your custom HW design or in the system/fpga synchronization method.
Thanks,
Richard
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