On Thu, Apr 02, 2015 at 11:40:28PM +0000, Daniel Le wrote:
> Thanks much for your help. I'll review the design. Meanwhile I have a couple
> more questions if you don't mind.
Regarding the design, it would be better to expose the FPGA clock to
ptp4l directly. That means letting ptp4l set and adjust the FPGA
clock. You don't have the PHC subsystem in your pre-3.0 kernel, but
you can emulate the interface in the FPGA driver using ioctls. For
the time stamps, you can hack your MAC driver to obtain the time
stamps and deliver them via so_timestamping.
> (1) Could you point me in the code where ptp4l slave clock sets for the first
> time the kernel CLOCK_REALTIME for SW time stamping? And I guess it does that
> right after transitioning into Slave state from Uncalibrated. I'm thinking
> the FPGA clock time should be stepped at that moment.
That happens in the function clock_synchronize() in clock.c,
switch (state) {
case SERVO_UNLOCKED:
break;
case SERVO_JUMP:
clockadj_set_freq(c->clkid, -adj);
clockadj_step(c->clkid, -tmv_to_nanoseconds(c->master_offset));
here. ----------^
...
case SERVO_LOCKED:
...
}
> (2) I tried to revert to sendto() and sk_receive() and ran into the following
> error messages:
>
> timed out while polling for tx timestamp
> increasing tx_timestamp_timeout may correct this issue, but it is
> likely caused by a driver bug
> port <portN>: send delay request failed
>
> Does that mean sendto() of the original program needs customization?
I am not sure what you have done to the kernel and user space code.
Without seeing the code, it is not possible for me to answer this
question.
Sorry,
Richard
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