Hi John, thank you for your reply. Yes, I have read your summery and followed the steps there, and also gone through the info in: https://sourceforge.net/p/linuxptp/mailman/linuxptp-users/thread/034101d2d661%24ccba5120%24662ef360%24%40foresys.com/#msg35861379
I am using kernel 4.1.22-ltsi-RT and 4.1.33-ltsi with these patches: https://github.com/torvalds/linux/commit/19d857c9038e5c07db8f8cc02b5ad0cd0098714f Did you have to do other changes on your 4.1.33-ltsi kernel than this? I have also tested with later kernel versions (4.18, 4.17 and 4.9 ltsi-RT), but they all generate various PTP related errors/issues in my system. BR AD > Sent: Thursday, October 18, 2018 at 4:05 PM > From: "John Lemonovich" <john.lemonov...@foresys.com> > To: "Arthur Dent" <arthurd...@cyberdude.com>, > linuxptp-users@lists.sourceforge.net > Subject: RE: [Linuxptp-users] LinuxPTP on Cyclone V SoC > > Arthur, > > > > Last year I was trying to get ptp working in an Arria10 SoC – and I > eventually got it all working pretty well. Eventually I went on to get it > working with an Intel FPGA 10GbE MAC for the A10 as well. The Cyclone V SoC > is very similar in that the HPS EMAC is actually the ST Micro MAC (stmmac), > which is supported by the Linux kernel and LinuxPTP for HW timestamping (see > table below). I made a post for exactly all the steps to make it work in my > A10. I was helped greatly by Ian Thompson and Hunter Olson, and they were > using the Cyclone V SoC. My A10 setup with clocking was a little different > in the Qsys editor and in the device tree, than for the Cyclone V. > > > > You can check out my summary here: > > https://sourceforge.net/p/linuxptp/mailman/message/35861379/ > > > > > > Hope this helps, > > > > > > John Lemonovich > > > > > > > > > > From: Arthur Dent <arthurd...@cyberdude.com> > Sent: Wednesday, October 17, 2018 3:31 PM > To: linuxptp-users@lists.sourceforge.net > Subject: [Linuxptp-users] LinuxPTP on Cyclone V SoC > > > > Hello > > I am trying to add PTP support on a Cyclone V SoC using the HPS EMAC1, but > have some problems making it work. > The problems seem to be related to a wrong clock source to the PTP engine > and/or device tree issues. I am using: > - Linux kernel 4.1.22 ltsi RT (real time) w/patches > - LinuxPTP 2.0 > > Steps taken: > 1: Compiling and installing linuxptp 2.0 > 2: In Quartus Qsys: The “Enable EMAC1 precision Time Protocol (PTP) FPGA > interface” box has been ticked, and this enables three PTP related signals: > - emac_ptp_ref_clock: This clock has been routed through the FPGA to an IO > pin on the development board, and is connected to an external clock source. > - ptp_pps_o: Routed through the FPGA to an IO pin on the development board > and is connected to a scope. > - the trig signal is unused (connected to GND) > 3: Updating the device tree: > > gmac1: ethernet@ff702000 { > ........ > clocks = <&emac1_clk &ext_clk_ptp_ref> ; > clock-names = "stmmaceth", "clk_ptp_ref"; > ..... > } > > Defining my external ptp clock source: > ext_clk_ptp_ref: ext_clk_ptp_ref{ > compatible = "fixed-clock"; > #clock-cells = <0>; > clock-frequency = <25000000>; /* 25.00 MHz */ > clock-output-names = "ext_clk_ptp_ref"; > }; > > 4: Running a Yocto Krogoth distribution with various version of the linux > kernel (4.18, 4.17, 4.9 ltsi-RT, and 4.1.22-ltsi-RT w/wo patches). > > None of these kernel versions work as expected in my system. > Kernel versions 4.17 and 4.18 do not seem to work at all, and I have ended > up using version 4.1.22.ltsi-RT (real time) kernel with the patches > recommended by "Hunter": > > <https://github.com/torvalds/linux/commit/19d857c9038e5c07db8f8cc02b5ad0cd0098714f> > > https://github.com/torvalds/linux/commit/19d857c9038e5c07db8f8cc02b5ad0cd0098714f > ref "Adding LinuxPTP to Arria 10 SoC" email. > > Output when running the "hwstamp_ctl -i eth0 -r 0 -t 1 " command: > Device driver does not have support for non-destructive SIOCGHWTSTAMP. > new settings: > tx_type 1 > rx_filter 0 > With the 4.1.22.ltsi-RT kernel and the command above I do get a 1PPS pulse > each sec as long as my ext_clk_ptp_ref in the device tree is specified to be > 25MHz. > However, the actual frequency of this signal can be anything so the PTP > engine does not seem to use my ext_clk_ptp_ref. > > > The "ptp4l -m -q -i eth0 ptp4l" command is not working: > ptp4l[193.348]: selected /dev/ptp0 as PTP clock > ptp4l[193.388]: port 1: INITIALIZING to LISTENING on INIT_COMPLETE > ptp4l[193.389]: port 0: INITIALIZING to LISTENING on INIT_COMPLETE > ptp4l[200.843]: port 1: LISTENING to MASTER on > ANNOUNCE_RECEIPT_TIMEOUT_EXPIRES > ptp4l[200.843]: selected local clock 70b3d5.fffe.761bc5 as best master > ptp4l[200.843]: assuming the grand master role > ptp4l[201.844]: timed out while polling for tx timestamp > ptp4l[201.845]: increasing tx_timestamp_timeout may correct this issue, > but it is likely caused by a driver bug > ptp4l[201.845]: port 1: send sync failed > ptp4l[201.845]: port 1: MASTER to FAULTY on FAULT_DETECTED > (FT_UNSPECIFIED) > > I have tried with various clocks sources (external and from the HPS) and > longer tx timestamp timeout setting, but without success. > > > > Is there anyone who has managed to get this working on a Cyclone V SoC > platform and can share some insight into how to connect the PTP signal in > Qsys and necessary device tree mappings? > > > Thanks, > AD > > _______________________________________________ Linuxptp-users mailing list Linuxptp-users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/linuxptp-users
