Phil,
ethtool -T eth0 reports:
Time stamping parameters for eth0:
Capabilities:
hardware-transmit (SOF_TIMESTAMPING_TX_HARDWARE)
software-transmit (SOF_TIMESTAMPING_TX_SOFTWARE)
hardware-receive (SOF_TIMESTAMPING_RX_HARDWARE)
software-receive (SOF_TIMESTAMPING_RX_SOFTWARE)
software-system-clock (SOF_TIMESTAMPING_SOFTWARE)
hardware-raw-clock (SOF_TIMESTAMPING_RAW_HARDWARE)
PTP Hardware Clock: 0
Hardware Transmit Timestamp Modes:
off (HWTSTAMP_TX_OFF)
on (HWTSTAMP_TX_ON)
Hardware Receive Filter Modes:
none (HWTSTAMP_FILTER_NONE)
all (HWTSTAMP_FILTER_ALL)
ptpv1-l4-event (HWTSTAMP_FILTER_PTP_V1_L4_EVENT)
ptpv1-l4-sync (HWTSTAMP_FILTER_PTP_V1_L4_SYNC)
ptpv1-l4-delay-req (HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ)
ptpv2-l4-event (HWTSTAMP_FILTER_PTP_V2_L4_EVENT)
ptpv2-l4-sync (HWTSTAMP_FILTER_PTP_V2_L4_SYNC)
ptpv2-l4-delay-req (HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ)
ptpv2-event (HWTSTAMP_FILTER_PTP_V2_EVENT)
ptpv2-sync (HWTSTAMP_FILTER_PTP_V2_SYNC)
ptpv2-delay-req (HWTSTAMP_FILTER_PTP_V2_DELAY_REQ)
(Sorry for the late reply, but l did not received your email. I have copied
your email from https://sourceforge.net/p/linuxptp/mailman/linuxptp-users/ and
added it below to keep the email thread.)
BR
AD
Re: [Linuxptp-users] LinuxPTP on Cyclone V SoC
From: Phil Reid <preid@el...> - 2018-12-06 03:07:08
On 6/12/2018 2:51 AM, Arthur Dent wrote:
> A brief update:
> On the Cyclone V SoC device the clk_ptp_ref can either be the internal emac
> clock (derivative of the osc1_clk) or an external clock (e.g. from the fpga).
> I need to use an external clock, but the stmmac drivers in kernel version
> 4.1.22 appears to only support the internal clock.
> This seems to be fixed in later kernel versions (e.g .4.18), but when using
> version 4.18 linuxptp generates error messages in my system:
> ptp4l -m -q -i eth0 -H -s:
> socfpga-dwmac ff702000.ethernet eth0: No support for HW time stamping
> ptp4l[36.915]: ioctl SIOCSHWTSTAMP failed: Operation not supported
> ptp4l[36.915]: port 1: INITIALIZING to FAULTY on FAULT_DETECTED
> (FT_UNSPECIFIED)
> ptp4l[36.915]: port 0: INITIALIZING to LISTENING on INIT_COMPLETE
G'day Arthir,
Haven't used the ptp functional for a while.
All used to work on the latest kernel for SocFPGA C-V.
What does "ethtool -T eth0" show for the capabilities?
--
Regards
Phil Reid
ElectroMagnetic Imaging Technology Pty Ltd
Development of Geophysical Instrumentation & Software
http://www.electromag.com.au
3 The Avenue, Midland WA 6056, AUSTRALIA
Ph: +61 8 9250 8100
Fax: +61 8 9250 7100
Email: preid@...
Sent: Wednesday, December 05, 2018 at 7:51 PM
From: "Arthur Dent" <arthurd...@cyberdude.com>
To: "Arthur Dent" <arthurd...@cyberdude.com>,
linuxptp-users@lists.sourceforge.net
Subject: Re: [Linuxptp-users] LinuxPTP on Cyclone V SoC
A brief update:
On the Cyclone V SoC device the clk_ptp_ref can either be the internal emac
clock (derivative of the osc1_clk) or an external clock (e.g. from the fpga).
I need to use an external clock, but the stmmac drivers in kernel version
4.1.22 appears to only support the internal clock.
This seems to be fixed in later kernel versions (e.g .4.18), but when using
version 4.18 linuxptp generates error messages in my system:
ptp4l -m -q -i eth0 -H -s:
socfpga-dwmac ff702000.ethernet eth0: No support for HW time stamping
ptp4l[36.915]: ioctl SIOCSHWTSTAMP failed: Operation not supported
ptp4l[36.915]: port 1: INITIALIZING to FAULTY on FAULT_DETECTED
(FT_UNSPECIFIED)
ptp4l[36.915]: port 0: INITIALIZING to LISTENING on INIT_COMPLETE
So I decided to keep the 4.1.22 version, and using 4.18 as a reference I hard
coded the 4.1.22 driver to use the external ptp clock.
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
old mode 100644
new mode 100755
index ae690dd..0aa52d6
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
@@ -236,8 +236,8 @@ static int socfpga_dwmac_setup(struct socfpga_dwmac
*dwmac)
int phymode = dwmac->interface;
u32 reg_offset = dwmac->reg_offset;
u32 reg_shift = dwmac->reg_shift;
- u32 ctrl, val;
-
+ u32 ctrl, val, module;
+
switch (phymode) {
case PHY_INTERFACE_MODE_RGMII:
case PHY_INTERFACE_MODE_RGMII_ID:
@@ -268,8 +268,16 @@ static int socfpga_dwmac_setup(struct socfpga_dwmac
*dwmac)
ctrl &= ~(SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << reg_shift);
ctrl |= val << reg_shift;
+ //Hard code ptp clock source to f2h_ptp_ref_clk
+ ctrl |= SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK << (reg_shift / 2);
+ regmap_read(sys_mgr_base_addr, SYSMGR_FPGAGRP_MODULE_REG,
+ &module);
+ module |= (SYSMGR_FPGAGRP_MODULE_EMAC << (reg_shift / 2));
+ regmap_write(sys_mgr_base_addr, SYSMGR_FPGAGRP_MODULE_REG,
+ module);
+
regmap_write(sys_mgr_base_addr, reg_offset, ctrl);
-
+
/* Deassert reset for the phy configuration to be sampled by
* the enet controller, and operation to start in requested mode
*/
Using this patch my system runs as expected. I.e. the PPS signal is locked to
the ptp reference clock coming from the FPGA.
/AD
Sent: Friday, October 19, 2018 at 12:51 PM
From: "Arthur Dent" <arthurd...@cyberdude.com>
To: "John Lemonovich" <john.lemonov...@foresys.com>,
linuxptp-users@lists.sourceforge.net
Subject: Re: [Linuxptp-users] LinuxPTP on Cyclone V SoC
Hi John, thank you for your reply.
Yes, I have read your summery and followed the steps there, and also gone
through the info in:
https://sourceforge.net/p/linuxptp/mailman/linuxptp-users/thread/034101d2d661%24ccba5120%24662ef360%24%40foresys.com/#msg35861379
I am using kernel 4.1.22-ltsi-RT and 4.1.33-ltsi with these patches:
https://github.com/torvalds/linux/commit/19d857c9038e5c07db8f8cc02b5ad0cd0098714f[https://github.com/torvalds/linux/commit/19d857c9038e5c07db8f8cc02b5ad0cd0098714f][https://github.com/torvalds/linux/commit/19d857c9038e5c07db8f8cc02b5ad0cd0098714f[https://github.com/torvalds/linux/commit/19d857c9038e5c07db8f8cc02b5ad0cd0098714f]]
Did you have to do other changes on your 4.1.33-ltsi kernel than this?
I have also tested with later kernel versions (4.18, 4.17 and 4.9 ltsi-RT), but
they all generate various PTP related errors/issues in my system.
BR
AD
> Sent: Thursday, October 18, 2018 at 4:05 PM
> From: "John Lemonovich" <john.lemonov...@foresys.com>
> To: "Arthur Dent" <arthurd...@cyberdude.com>,
> linuxptp-users@lists.sourceforge.net
> Subject: RE: [Linuxptp-users] LinuxPTP on Cyclone V SoC
>
> Arthur,
>
>
>
> Last year I was trying to get ptp working in an Arria10 SoC – and I
> eventually got it all working pretty well. Eventually I went on to get it
> working with an Intel FPGA 10GbE MAC for the A10 as well. The Cyclone V SoC
> is very similar in that the HPS EMAC is actually the ST Micro MAC (stmmac),
> which is supported by the Linux kernel and LinuxPTP for HW timestamping (see
> table below). I made a post for exactly all the steps to make it work in my
> A10. I was helped greatly by Ian Thompson and Hunter Olson, and they were
> using the Cyclone V SoC. My A10 setup with clocking was a little different
> in the Qsys editor and in the device tree, than for the Cyclone V.
>
>
>
> You can check out my summary here:
>
> https://sourceforge.net/p/linuxptp/mailman/message/35861379/[https://sourceforge.net/p/linuxptp/mailman/message/35861379/][https://sourceforge.net/p/linuxptp/mailman/message/35861379/[https://sourceforge.net/p/linuxptp/mailman/message/35861379/]]
>
>
>
>
>
> Hope this helps,
>
>
>
>
>
> John Lemonovich
>
>
>
>
>
>
>
>
>
> From: Arthur Dent <arthurd...@cyberdude.com>
> Sent: Wednesday, October 17, 2018 3:31 PM
> To: linuxptp-users@lists.sourceforge.net
> Subject: [Linuxptp-users] LinuxPTP on Cyclone V SoC
>
>
>
> Hello
>
> I am trying to add PTP support on a Cyclone V SoC using the HPS EMAC1, but
> have some problems making it work.
> The problems seem to be related to a wrong clock source to the PTP engine
> and/or device tree issues. I am using:
> - Linux kernel 4.1.22 ltsi RT (real time) w/patches
> - LinuxPTP 2.0
>
> Steps taken:
> 1: Compiling and installing linuxptp 2.0
> 2: In Quartus Qsys: The “Enable EMAC1 precision Time Protocol (PTP) FPGA
> interface” box has been ticked, and this enables three PTP related signals:
> - emac_ptp_ref_clock: This clock has been routed through the FPGA to an IO
> pin on the development board, and is connected to an external clock source.
> - ptp_pps_o: Routed through the FPGA to an IO pin on the development board
> and is connected to a scope.
> - the trig signal is unused (connected to GND)
> 3: Updating the device tree:
>
> gmac1: ethernet@ff702000 {
> ........
> clocks = <&emac1_clk &ext_clk_ptp_ref> ;
> clock-names = "stmmaceth", "clk_ptp_ref";
> .....
> }
>
> Defining my external ptp clock source:
> ext_clk_ptp_ref: ext_clk_ptp_ref{
> compatible = "fixed-clock";
> #clock-cells = <0>;
> clock-frequency = <25000000>; /* 25.00 MHz */
> clock-output-names = "ext_clk_ptp_ref";
> };
>
> 4: Running a Yocto Krogoth distribution with various version of the linux
> kernel (4.18, 4.17, 4.9 ltsi-RT, and 4.1.22-ltsi-RT w/wo patches).
>
> None of these kernel versions work as expected in my system.
> Kernel versions 4.17 and 4.18 do not seem to work at all, and I have ended
> up using version 4.1.22.ltsi-RT (real time) kernel with the patches
> recommended by "Hunter":
> <https://github.com/torvalds/linux/commit/19d857c9038e5c07db8f8cc02b5ad0cd0098714f[https://github.com/torvalds/linux/commit/19d857c9038e5c07db8f8cc02b5ad0cd0098714f][https://github.com/torvalds/linux/commit/19d857c9038e5c07db8f8cc02b5ad0cd0098714f[https://github.com/torvalds/linux/commit/19d857c9038e5c07db8f8cc02b5ad0cd0098714f]]>
> https://github.com/torvalds/linux/commit/19d857c9038e5c07db8f8cc02b5ad0cd0098714f[https://github.com/torvalds/linux/commit/19d857c9038e5c07db8f8cc02b5ad0cd0098714f][https://github.com/torvalds/linux/commit/19d857c9038e5c07db8f8cc02b5ad0cd0098714f[https://github.com/torvalds/linux/commit/19d857c9038e5c07db8f8cc02b5ad0cd0098714f]]
> ref "Adding LinuxPTP to Arria 10 SoC" email.
>
> Output when running the "hwstamp_ctl -i eth0 -r 0 -t 1 " command:
> Device driver does not have support for non-destructive SIOCGHWTSTAMP.
> new settings:
> tx_type 1
> rx_filter 0
> With the 4.1.22.ltsi-RT kernel and the command above I do get a 1PPS pulse
> each sec as long as my ext_clk_ptp_ref in the device tree is specified to be
> 25MHz.
> However, the actual frequency of this signal can be anything so the PTP
> engine does not seem to use my ext_clk_ptp_ref.
>
>
> The "ptp4l -m -q -i eth0 ptp4l" command is not working:
> ptp4l[193.348]: selected /dev/ptp0 as PTP clock
> ptp4l[193.388]: port 1: INITIALIZING to LISTENING on INIT_COMPLETE
> ptp4l[193.389]: port 0: INITIALIZING to LISTENING on INIT_COMPLETE
> ptp4l[200.843]: port 1: LISTENING to MASTER on
> ANNOUNCE_RECEIPT_TIMEOUT_EXPIRES
> ptp4l[200.843]: selected local clock 70b3d5.fffe.761bc5 as best master
> ptp4l[200.843]: assuming the grand master role
> ptp4l[201.844]: timed out while polling for tx timestamp
> ptp4l[201.845]: increasing tx_timestamp_timeout may correct this issue,
> but it is likely caused by a driver bug
> ptp4l[201.845]: port 1: send sync failed
> ptp4l[201.845]: port 1: MASTER to FAULTY on FAULT_DETECTED
> (FT_UNSPECIFIED)
>
> I have tried with various clocks sources (external and from the HPS) and
> longer tx timestamp timeout setting, but without success.
>
>
>
> Is there anyone who has managed to get this working on a Cyclone V SoC
> platform and can share some insight into how to connect the PTP signal in
> Qsys and necessary device tree mappings?
>
>
> Thanks,
> AD
>
>
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