https://github.com/Qwinci updated https://github.com/llvm/llvm-project/pull/214034
>From 3166620806b2a0f0260694fbb099bab9398594da Mon Sep 17 00:00:00 2001 From: Qwinci <[email protected]> Date: Tue, 4 Aug 2026 20:43:16 +0300 Subject: [PATCH] [lldb][RISCV] Add float register ABI stubs This allows retrieving the float registers for other frames from e.g. QEMU gdbstub via DWARF rules. --- .../Plugins/ABI/RISCV/ABISysV_riscv.cpp | 70 ++++++++++++++- lldb/unittests/ABI/CMakeLists.txt | 4 + lldb/unittests/ABI/RISCV/ABIRISCVTest.cpp | 86 +++++++++++++++++++ lldb/unittests/ABI/RISCV/CMakeLists.txt | 9 ++ 4 files changed, 166 insertions(+), 3 deletions(-) create mode 100644 lldb/unittests/ABI/RISCV/ABIRISCVTest.cpp create mode 100644 lldb/unittests/ABI/RISCV/CMakeLists.txt diff --git a/lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.cpp b/lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.cpp index 19bbef9c4119e..7443adf764816 100644 --- a/lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.cpp +++ b/lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.cpp @@ -83,10 +83,42 @@ enum regnums { t4, t5, t6, - pc + pc = riscv_dwarf::dwarf_gpr_pc, + ft0 = riscv_dwarf::dwarf_fpr_f0, + ft1, + ft2, + ft3, + ft4, + ft5, + ft6, + ft7, + fs0, + fs1, + fa0, + fa1, + fa2, + fa3, + fa4, + fa5, + fa6, + fa7, + fs2, + fs3, + fs4, + fs5, + fs6, + fs7, + fs8, + fs9, + fs10, + fs11, + ft8, + ft9, + ft10, + ft11 }; -static const std::array<RegisterInfo, 33> g_register_infos = { +static const std::array<RegisterInfo, 65> g_register_infos = { {DEFINE_REGISTER_STUB(zero, nullptr), DEFINE_GENERIC_REGISTER_STUB(ra, nullptr, LLDB_REGNUM_GENERIC_RA), DEFINE_GENERIC_REGISTER_STUB(sp, nullptr, LLDB_REGNUM_GENERIC_SP), @@ -119,7 +151,39 @@ static const std::array<RegisterInfo, 33> g_register_infos = { DEFINE_REGISTER_STUB(t4, nullptr), DEFINE_REGISTER_STUB(t5, nullptr), DEFINE_REGISTER_STUB(t6, nullptr), - DEFINE_GENERIC_REGISTER_STUB(pc, nullptr, LLDB_REGNUM_GENERIC_PC)}}; + DEFINE_GENERIC_REGISTER_STUB(pc, nullptr, LLDB_REGNUM_GENERIC_PC), + DEFINE_REGISTER_STUB(ft0, nullptr), + DEFINE_REGISTER_STUB(ft1, nullptr), + DEFINE_REGISTER_STUB(ft2, nullptr), + DEFINE_REGISTER_STUB(ft3, nullptr), + DEFINE_REGISTER_STUB(ft4, nullptr), + DEFINE_REGISTER_STUB(ft5, nullptr), + DEFINE_REGISTER_STUB(ft6, nullptr), + DEFINE_REGISTER_STUB(ft7, nullptr), + DEFINE_REGISTER_STUB(fs0, nullptr), + DEFINE_REGISTER_STUB(fs1, nullptr), + DEFINE_REGISTER_STUB(fa0, nullptr), + DEFINE_REGISTER_STUB(fa1, nullptr), + DEFINE_REGISTER_STUB(fa2, nullptr), + DEFINE_REGISTER_STUB(fa3, nullptr), + DEFINE_REGISTER_STUB(fa4, nullptr), + DEFINE_REGISTER_STUB(fa5, nullptr), + DEFINE_REGISTER_STUB(fa6, nullptr), + DEFINE_REGISTER_STUB(fa7, nullptr), + DEFINE_REGISTER_STUB(fs2, nullptr), + DEFINE_REGISTER_STUB(fs3, nullptr), + DEFINE_REGISTER_STUB(fs4, nullptr), + DEFINE_REGISTER_STUB(fs5, nullptr), + DEFINE_REGISTER_STUB(fs6, nullptr), + DEFINE_REGISTER_STUB(fs7, nullptr), + DEFINE_REGISTER_STUB(fs8, nullptr), + DEFINE_REGISTER_STUB(fs9, nullptr), + DEFINE_REGISTER_STUB(fs10, nullptr), + DEFINE_REGISTER_STUB(fs11, nullptr), + DEFINE_REGISTER_STUB(ft8, nullptr), + DEFINE_REGISTER_STUB(ft9, nullptr), + DEFINE_REGISTER_STUB(ft10, nullptr), + DEFINE_REGISTER_STUB(ft11, nullptr)}}; } // namespace dwarf } // namespace diff --git a/lldb/unittests/ABI/CMakeLists.txt b/lldb/unittests/ABI/CMakeLists.txt index 8ad7474e9444a..27f3c300f3945 100644 --- a/lldb/unittests/ABI/CMakeLists.txt +++ b/lldb/unittests/ABI/CMakeLists.txt @@ -1,3 +1,7 @@ if ("AArch64" IN_LIST LLVM_TARGETS_TO_BUILD) add_subdirectory(AArch64) endif() + +if ("RISCV" IN_LIST LLVM_TARGETS_TO_BUILD) + add_subdirectory(RISCV) +endif() diff --git a/lldb/unittests/ABI/RISCV/ABIRISCVTest.cpp b/lldb/unittests/ABI/RISCV/ABIRISCVTest.cpp new file mode 100644 index 0000000000000..9ccf75b14621e --- /dev/null +++ b/lldb/unittests/ABI/RISCV/ABIRISCVTest.cpp @@ -0,0 +1,86 @@ +//===-- ABIRISCVTest.cpp --------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "Plugins/ABI/RISCV/ABISysV_riscv.h" +#include "Utility/RISCV_DWARF_Registers.h" +#include "lldb/Target/DynamicRegisterInfo.h" +#include "lldb/Utility/ArchSpec.h" +#include "llvm/Support/ManagedStatic.h" +#include "llvm/Support/TargetSelect.h" +#include "gtest/gtest.h" +#include <vector> + +using namespace lldb_private; +using namespace lldb; + +class ABIRISCVTestFixture : public testing::TestWithParam<llvm::StringRef> { +public: + static void SetUpTestCase(); + static void TearDownTestCase(); +}; + +void ABIRISCVTestFixture::SetUpTestCase() { + LLVMInitializeRISCVTargetInfo(); + LLVMInitializeRISCVTargetMC(); + ABISysV_riscv::Initialize(); +} + +void ABIRISCVTestFixture::TearDownTestCase() { + ABISysV_riscv::Terminate(); + llvm::llvm_shutdown(); +} + +static DynamicRegisterInfo::Register MakeRegister(const char *name) { + DynamicRegisterInfo::Register reg; + reg.name = ConstString(name); + reg.set_name = ConstString("GPR"); + return reg; +} + +TEST_P(ABIRISCVTestFixture, AugmentRegisterInfo) { + ABISP abi_sp = ABI::FindPlugin(ProcessSP(), ArchSpec(GetParam())); + ASSERT_TRUE(abi_sp); + + std::vector<DynamicRegisterInfo::Register> regs{ + MakeRegister("ra"), MakeRegister("sp"), MakeRegister("pc")}; + abi_sp->AugmentRegisterInfo(regs); + + ASSERT_EQ(regs.size(), 3U); + EXPECT_EQ(regs[0].regnum_dwarf, riscv_dwarf::dwarf_gpr_ra); + EXPECT_EQ(regs[0].regnum_ehframe, riscv_dwarf::dwarf_gpr_ra); + EXPECT_EQ(regs[1].regnum_dwarf, riscv_dwarf::dwarf_gpr_sp); + EXPECT_EQ(regs[2].regnum_dwarf, riscv_dwarf::dwarf_gpr_pc); + EXPECT_EQ(regs[2].regnum_generic, + static_cast<uint32_t>(LLDB_REGNUM_GENERIC_PC)); +} + +TEST_P(ABIRISCVTestFixture, AugmentRegisterInfoFloatingPoint) { + ABISP abi_sp = ABI::FindPlugin(ProcessSP(), ArchSpec(GetParam())); + ASSERT_TRUE(abi_sp); + + std::vector<DynamicRegisterInfo::Register> regs{ + MakeRegister("ft0"), MakeRegister("fs0"), MakeRegister("fs1"), + MakeRegister("fa0"), MakeRegister("fs2"), MakeRegister("fs11"), + MakeRegister("ft11")}; + abi_sp->AugmentRegisterInfo(regs); + + ASSERT_EQ(regs.size(), 7U); + EXPECT_EQ(regs[0].regnum_dwarf, riscv_dwarf::dwarf_fpr_f0); + EXPECT_EQ(regs[0].regnum_ehframe, riscv_dwarf::dwarf_fpr_f0); + EXPECT_EQ(regs[1].regnum_dwarf, riscv_dwarf::dwarf_fpr_f8); + EXPECT_EQ(regs[2].regnum_dwarf, riscv_dwarf::dwarf_fpr_f9); + EXPECT_EQ(regs[3].regnum_dwarf, riscv_dwarf::dwarf_fpr_f10); + EXPECT_EQ(regs[4].regnum_dwarf, riscv_dwarf::dwarf_fpr_f18); + EXPECT_EQ(regs[5].regnum_dwarf, riscv_dwarf::dwarf_fpr_f27); + EXPECT_EQ(regs[6].regnum_dwarf, riscv_dwarf::dwarf_fpr_f31); + EXPECT_EQ(regs[6].regnum_ehframe, riscv_dwarf::dwarf_fpr_f31); +} + +INSTANTIATE_TEST_SUITE_P(ABIRISCVTests, ABIRISCVTestFixture, + testing::Values("riscv64-unknown-linux-gnu", + "riscv32-unknown-linux-gnu")); diff --git a/lldb/unittests/ABI/RISCV/CMakeLists.txt b/lldb/unittests/ABI/RISCV/CMakeLists.txt new file mode 100644 index 0000000000000..338ded9a3c881 --- /dev/null +++ b/lldb/unittests/ABI/RISCV/CMakeLists.txt @@ -0,0 +1,9 @@ +add_lldb_unittest(ABIRISCVTests + ABIRISCVTest.cpp + LINK_COMPONENTS + Support + RISCV + LINK_LIBS + lldbTarget + lldbPluginABIRISCV + ) _______________________________________________ lldb-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
