Qwinci wrote: I've updated the commit/PR description with more detail as it was a bit misleading, its not directly about the registers themself but specifically DWARF rules referencing the registers. Without this patch trying to read a variable that is stored in a callee-saved float register (fs0-fs11) within the parent frame of a called function that uses the same float register would error (`unable to convert register kind=1 reg_num=40 to a native register number`). I've added a register augmentation test similar to the AArch64 one for RISCV that tests that the registers are properly resolved from their names (which is what e.g. QEMU gdbstub gives).
https://github.com/llvm/llvm-project/pull/214034 _______________________________________________ lldb-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
