================
@@ -760,6 +772,61 @@ def test_riscv64_regs(self):
self.expect("register read --all")
+ @skipIfLLVMTargetMissing("RISCV")
----------------
DavidSpickett wrote:
I'm saying that if risc-v grows a lot of strange register state, it will be
better served by separate test cases.
For this PR, just consider renaming the test functions here so that they list
what they are testing. So riscv64_gpr, as opposed to to riscv64_nofpr.
https://github.com/llvm/llvm-project/pull/104547
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